Using the VIC port to acknowledge the servicing of an IRQ interrupt reduces the interrupt latency, because the processor does not need to do an AHB access to obtain the address for the ISR. The speed of the handshaking between the VIC and processor depends on the clock frequencies used, and whether the clocks are synchronous or asynchronous. Because the timing for each core differs, see the relevant ARM processor Technical Reference Manual for information on the instruction cycle times. The processor used and its configuration also influence the time for the interrupts to be serviced.

The ARM architecture defines several exceptions to be handled by the processor. The two exceptions that are the main concern are the interrupt and fast interrupt exceptions, triggered by the IRQ and FIQ signals respectively.

The IRQ and FIQ signals are generated by the VIC external to the ARM core to signal real-world events. The speed of response to these signals is known as interrupt latency. The factors influencing interrupt latency are described in this section, using an FIQ as an example.

Interrupt latency is described in more detail in the following sections: