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| Home > Programmer’s Model for Test > Test registers > Integration Test Output Register 2, VICITOP2 |
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| Home > Programmer’s Model for Test > Test registers > Integration Test Output Register 2, VICITOP2 |
VICITOP2 is a 32-bit register that controls the VICVECTADDROUT output. This register must only be used in test mode. The register can be accessed with zero wait states.
Table 4.6 shows the bit assignment of the VICITOP2 Register.
Table 4.6. VICITOP2 Register bit assignments
Bits | Name | Type | Description |
|---|---|---|---|
[31:0] | VICVECTADDROUT | Read/ write | Read the value of the VICVECTADDROUT output when the VICITCR ITEN bit is LOW. Read the value of this field when the VICITCR ITEN bit is HIGH. Write sets output to written value when the VICITCR ITEN bit is HIGH. |
| Copyright © 2002 ARM Limited. All rights reserved. | ARM DDI 0273A |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model for Test > Test registers > Integration Test Output Register 2, VICITOP2 |