| Copyright © 2002 ARM Limited. All rights reserved. | ARM DDI 0273A |
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| Home > Programmer’s Model for Test > Test registers > Integration Test Output Register 1, VICITOP1 |
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| Home > Programmer’s Model for Test > Test registers > Integration Test Output Register 1, VICITOP1 |
VICITOP1 is a 4-bit register that is used to control and read the values of the following outputs:
nVICIRQ
nVICFIQ
VICVECTADDRV
VICIRQACKOUT.
This register must only be used in test mode. The read value in VICITOP1 always takes two clock cycles to update, because of the use of dual flip-flop synchronization logic that avoids metastability problems. For example, when a new value is written into this register, an immediate read from the register returns the old value. After two cycles, a read from this register returns the updated value. The register can be accessed with zero wait states.
Table 4.5 shows the bit assignment of the VICITOP1 Register.
Table 4.5. VICITOP1 Register bit assignments
Bits | Name | Type | Description |
|---|---|---|---|
[31:10] | Reserved | - | Reserved, read as zero, do not modify. |
[9] | VICIRQACKOUT | Read/ write | Read the value of the VICIRQACKOUT output when the VICITCR ITEN bit is LOW. Read the value of this field when the VICITCR ITEN bit is HIGH. Write sets output to written value when the VICITCR ITEN bit is HIGH. |
[8] | VICVECTADDRV | Read/ write | Read the value of the VICVECTADDRV output when the VICITCR ITEN bit is LOW. Read the value of this field when the VICITCR ITEN bit is HIGH. Write sets output to written value when the VICITCR ITEN bit is HIGH. |
[7] | VICIRQ | Read/ write | Read the value of the internal VICIRQ signal when the VICITCR ITEN bit is LOW. This is the pre-inverted version of the final output, and is inverted to create the final nVICIRQ output. Read the value of this field when the VICITCR ITEN bit is HIGH. Write sets output to written value when the VICITCR ITEN bit is HIGH. |
[6] | VICFIQ | Read/ write | Read the value of the internal VICFIQ signal when the VICITCR ITEN bit is LOW. This is the pre-inverted version of the final output, and is inverted to create the final nVICFIQ output. Read the value of this field when the VICITCR ITEN bit is HIGH. Write sets output to written value when the VICITCR ITEN bit is HIGH. |
[5:0] | Reserved | - | Reserved, read as zero, do not modify. |
| Copyright © 2002 ARM Limited. All rights reserved. | ARM DDI 0273A |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model for Test > Test registers > Integration Test Output Register 1, VICITOP1 |