In synchronous mode, the ARM11 and ARM1026EJ processors can run at any multiple of the bus clock frequency. The interface between the ARM11 and ARM1026EJ processor and VIC handles this by using handshaking.

Figure 2.12 shows the minimum timing for an active IRQ when the processor and bus clocks are the same.

When the CPU detects the nIRQ signal is active, it asserts the VICIRQACK input at bus clock time B5 to indicate that it is ready to service the interrupt. The time taken for the CPU to respond to the interrupt depends on the current state of the processor, but the interrupt is always synchronized so the timing shown is the minimum possible. The VIC then asserts the output VICVECTADDRV, indicating that the value on the address bus is stable and does not change until after the processor acknowledges sampling the address value (to avoid a higher priority interrupt changing the address value). The vector address is sampled by the processor at B7, when it has detected that VICVECTADDRV is asserted. VICIRQACK is then deasserted, and one cycle later both VICVECTADDRV and nIRQ are deasserted to prevent the processor sampling the IRQ a second time before the VIC has cleared the interrupt. The processor only samples nIRQ while VICVECTADDRV is deasserted.

Figure 2.13 shows the basic timing for an active IRQ when the processor clock is twice the frequency of the bus clock, and the interrupt acknowledge is asserted on the falling edge of the bus clock.

Because the processor clock is running at twice the speed of the bus clock, the VICIRQACK response from the processor is valid earlier than when the processor and bus clocks are the same, at time P8. The VICVECTADDRV output is asserted at time B6 after the address has been generated and the processor acknowledge has been detected. This is the same as when the clocks are at the same frequency, because of the synchronization logic required on the nIRQ path. The vector address value is then sampled on processor clock edge P12, and the acknowledge is deasserted. The nIRQ and address valid outputs are deasserted on bus clock edge B7, after the acknowledge signal has been sampled.

VICVECTADDR[31:0] is generated from nIRQ which is then synchronized to the bus clock (two clock cycles) and then though the priority logic (one clock cycle) into the address generation logic which produces the address.