| Copyright © 2002 ARM Limited. All rights reserved. | ARM DDI 0273A |
| Non-Confidential | |
 PDF version | |
| Home > Programmer’s Model > Register descriptions > Vector Priority Registers, VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY |
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| Home > Programmer’s Model > Register descriptions > Vector Priority Registers, VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY |
The VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY Registers select the interrupt priority level for the 32 vectored interrupt sources, and the daisy chain input. The value can be from 0-15. The default values have all interrupts on the same priority level, 15, which is the lowest. This enables any of the vectored interrupts to be promoted to a higher priority with one simple register write. These registers can be accessed with one wait state.
Table 3.14 shows the bit assignment of the VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY Registers.
Table 3.14. VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY Register bit assignments
Bits | Name | Type | Function |
|---|---|---|---|
[31:4] | Reserved | - | Reserved, read as zero, do not modify. |
[3:0] | VectPriority | Read/write | Selects vectored interrupt priority level. You can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0-15. |
Hardware priority levels only take effect when multiple interrupts are programmed to have the same priority level and occur at the same time. In this case, vectored interrupt 0 has the highest priority, and interrupt 31 has the lowest priority.
If the VIC is used as part of a daisy-chain configuration in VIC0 mode, ensure that the interrupt service routine does not change the VICVECTPRIORITYDAISY register to a higher priority.
| Copyright © 2002 ARM Limited. All rights reserved. | ARM DDI 0273A |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Register descriptions > Vector Priority Registers, VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY |