3.3.15. PrimeCell Identification Registers, VICPCELLID0-3

The VICPCELLID0-3 Registers are four 8-bit registers, that span address locations 0xFF0-0xFFC. The read-only register can conceptually be treated as a single 32-bit register. The register is used as a standard cross-peripheral identification system. Figure 3.2 shows the bit assignment for the VICPCELLID0-3 Registers.

Figure 3.2. PrimeCell Identification Register bit assignment

The four 8-bit registers are described in the following subsections:

VICPCELLID0 Register

The VICPCELLID0 Register is hard-coded and the fields within the register determine the reset value. Table 3.19 shows the bit assignment of the VICPCELLID0 Register.

Table 3.19. VICPCELLID0 Register bit assignments

Bits

Name

Type

Function

[31:8]

-

-

Reserved, read as zero, do not modify.

[7:0]

VICPCellID0

Read

These bits read back as 0x0D.

VICPCELLID1 Register

The VICPCELLID1 Register is hard-coded and the fields within the register determine the reset value. Table 3.20 shows the bit assignment of the VICPCELLID1 Register.

Table 3.20. VICPCELLID1 Register bit assignments

Bits

Name

Type

Function

[31:8]

-

-

Reserved, read as zero, do not modify.

[7:0]

VICPCellID1

Read

These bits read back as 0xF0.

VICPCELLID2 Register

The VICPCELLID2 Register is hard-coded and the fields within the register determine the reset value. Table 3.21 shows the bit assignment of the VICPCELLID2 Register.

Table 3.21. VICPCELLID2 Register bit assignments

Bits

Name

Type

Function

[31:8]

-

-

Reserved, read as zero, do not modify.

[7:0]

VICPCellID2

Read

These bits read back as 0x05.

VICPCELLID3 Register

The VICPCELLID3 Register is hard-coded and the fields within the register determine the reset value. Table 3.22 shows the bit assignment of the VICPCELLID3 Register.

Table 3.22. VICPCELLID3 Register bit assignments

Bits

Name

Type

Function

[31:8]

-

-

Reserved, read as zero, do not modify.

[7:0]

VICPCellID3

Read

These bits read back as 0xB1.

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