ARM PrimeCell™ Vectored Interrupt Controller (PL192) Technical Reference Manual 3.3.6. Interrupt Enable Clear Register, VICINTENCLEAR

3.3.6. Interrupt Enable Clear Register, VICINTENCLEAR

The VICINTENCLEAR Register clears bits in the VICINTENABLE Register, and masks out the interrupt sources for the IRQ interrupt. This register can be accessed with zero wait states.

Table 3.7 shows the bit assignment of the VICINTENCLEAR Register.

Table 3.7. VICINTENCLEAR Register bit assignments

Bits	Name	Type	Function
[31:0]	IntEnable Clear	Write	Clears corresponding bits in the VICINTENABLE Register: 0 = no effect 1 = interrupt disabled in VICINTENABLE Register. There is one bit of the register for each interrupt source.

Bits

Name

Type

Function

[31:0]

IntEnable Clear

Write

Clears corresponding bits in the VICINTENABLE Register:

0 = no effect

1 = interrupt disabled in VICINTENABLE Register.

There is one bit of the register for each interrupt source.

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