To ensure that the Vector Address Register (see Vector Address Register, VICADDRESS) can be read in a single instruction, the PrimeCell VIC base address must be 0xFFFFF000, the upper 4K of memory. Placing the PrimeCell VIC anywhere else in memory increases interrupt latency because the ARM processor is unable to access the VICADDRESS Register using a single instruction.

The read (LDR) instruction has a maximum address offset of 12 bits, equivalent to 4K, meaning that it can read from an address up to 4K away from the current address with a single read instruction. If the address to be read from is more than 4K away, a second instruction is required to read in the full address value, and takes longer to be performed.

When an interrupt occurs, the current address is either the IRQ or FIQ exception vector location (0x00000018 or 0x0000001C for normal low exception vectors). A 4K offset from the exception address is the upper 4K of memory, so placing the VIC in this area of memory allows the read of the VICADDRESS Register (at 0xFFFFFF00) to be performed using an address offset with a single instruction. For example at location 0x18 LDR pc, [pc, #-0x120] to access VICADDRESS at location 0xFFFFFF00.

If a processor supporting high exception vectors is used and the HIVECS configuration pin is tied HIGH, the VIC must be located at 0xFFFEF000 to allow for the exception vectors which are located at 0xFFFFF000. The VIC is not located at 0x00000000, because this is the standard location for the system memory.

The offset of any particular register from the base address is fixed.