3.3. Register descriptions
The following registers are described in this section:
IRQ Status Register, VICIRQSTATUS
FIQ Status Register, VICFIQSTATUS
Raw Interrupt Status Register, VICRAWINTR
Interrupt Select Register, VICINTSELECT
Interrupt Enable Register, VICINTENABLE
Interrupt Enable Clear Register, VICINTENCLEAR
Software Interrupt Register, VICSOFTINT
Software Interrupt Clear Register,
VICSOFTINTCLEAR
Protection Enable Register, VICPROTECTION
Vector Address Register, VICADDRESS
Software Priority Mask Register, VICSWPRIORITYMASK
Vector Address Registers, VICVECTADDR[0-31]
Vector Priority Registers, VICVECTPRIORITY[0-31]
and VICVECTPRIORITYDAISY
Peripheral Identification Registers,
VICPERIPHID0-3
PrimeCell Identification Registers,
VICPCELLID0-3.
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