HCLK

Input

Clock source

AMBA AHB bus clock, used to time all bus transfers. All signal timings are related to the rising edge of HCLK.

HRESETn

Input

Reset controller

AHB bus reset, active LOW.

HADDR[11:2]

Input

Master

System address bus.

HTRANS[1:0]

Input

Master

Transfer type, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY. This signal must be connected to HTRANS[1] on the AHB interface. HTRANS[0] is not used.

HWRITE

Input

Master

Transfer direction. Indicates a write transfer when HIGH, and a read transfer when LOW.

HSIZE[2:0]

Input

Master

Size of the transfer, which must be word (32-bit) for the VIC (HSIZE[2:0] = 0b010).

HPROT[3:0]

Input

Master

Memory access protection type, which can be User mode (0) or privileged mode (1). This signal must be connected to HPROT[1] on the AHB interface. HPROT[3], HPROT[2] and HPROT[0] are not used.

HWDATA[31:0]

Input

Master

Write data bus, used to transfer data from bus master to bus slaves during write operations.

HSELVIC

Input

Decoder

Slave select signal, which is a combinatorial decode of the address bus. It indicates that the current transfer is intended for the selected slave.

HRDATA[31:0]

Output

Slave

Read data bus, used to transfer data from bus slaves to bus master during read operations.

HREADYIN

Input

External slave

Transfer done signal, generated by an alternate slave. When HIGH, indicates that a transfer is complete. Can be driven LOW to extend a transfer.

HREADYOUT

Output

Slave

Transfer done signal, generated by the VIC. When HIGH, indicates that a transfer is complete. Can be driven LOW to extend a transfer.

HRESP[1:0]

Input

Slave

Transfer response, which provides additional transfer status information. The response can be OKAY, ERROR, RETRY or SPLIT. The PrimeCell VIC responds with either OKAY or ERROR.