ARM PrimeCell ™ VectoredInterrupt Controller (PL192) Technical Reference Manual

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ARM PrimeCell ™ VectoredInterrupt Controller (PL192) Technical Reference Manual

Copyright © 2002 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

About this document

Intended audience
Organization
Typographical conventions

Further reading

ARM publications

Feedback on the ARM PrimeCell VectoredInterrupt Controller (PL192)
Feedback on this document

1. Introduction

1.1. About the ARM PrimeCell Vectored InterruptController (PL192)

1.1.1. Features of the PrimeCell VIC

1.2. Release information

2. Functional Overview

2.1. PrimeCell VIC overview

2.1.1. Interrupt request logic
2.1.2. Nonvectored FIQ interrupt logic
2.1.3. Vectored IRQ interrupt logic
2.1.4. Interrupt priority logic
2.1.5. Interrupt priority masking
2.1.6. Vectored interrupts
2.1.7. Software interrupts
2.1.8. Interrupt service routine addresses

2.2. Operation

2.2.1. Vectored interrupt flow sequence usingAHB
2.2.2. Nonvectored interrupt flow sequenceusing AHB
2.2.3. FIQ interrupt flow sequence
2.2.4. Vectored IRQ interrupt flow sequenceusing VIC port

2.3. Connectivity

2.3.1. Single interrupt controller connectivityto a processor without VIC port
2.3.2. Daisy-chained interrupt controllerconnectivity to processor without VIC port
2.3.3. Daisy-chained VIC mode
2.3.4. VIC port connections
2.3.5. Synchronous mode VIC port timing
2.3.6. Asynchronous mode VIC port timing

3. Programmer’s Model

3.1. About the programmer’s model

3.2. Summary of PrimeCell VIC registers

3.3. Register descriptions

3.3.1. IRQ Status Register, VICIRQSTATUS
3.3.2. FIQ Status Register, VICFIQSTATUS
3.3.3. Raw Interrupt Status Register, VICRAWINTR
3.3.4. Interrupt Select Register, VICINTSELECT
3.3.5. Interrupt Enable Register, VICINTENABLE
3.3.6. Interrupt Enable Clear Register, VICINTENCLEAR
3.3.7. Software Interrupt Register, VICSOFTINT
3.3.8. Software Interrupt Clear Register,VICSOFTINTCLEAR
3.3.9. Protection Enable Register, VICPROTECTION
3.3.10. Vector Address Register, VICADDRESS
3.3.11. Software Priority Mask Register, VICSWPRIORITYMASK
3.3.12. Vector Address Registers, VICVECTADDR[0-31]
3.3.13. Vector Priority Registers, VICVECTPRIORITY[0-31]and VICVECTPRIORITYDAISY
3.3.14. Peripheral Identification Registers,VICPERIPHID0-3
3.3.15. PrimeCell Identification Registers,VICPCELLID0-3

3.4. Interrupt latency

3.4.1. Core latency
3.4.2. Memory systems and cycle types
3.4.3. Tightly-coupled memory
3.4.4. Caches
3.4.5. Compiler optimizations

3.5. Example interrupt latency calculations

3.5.1. ARM7TDMI FIQ interrupt latency duringLDM
3.5.2. ARM9 FIQ interrupt latency duringLDM
3.5.3. ARM10 FIQ interrupt latency duringLDM
3.5.4. Interrupts in ARM1026EJ and ARM11cores
3.5.5. IRQ during IRQ in an example ARMv5system
3.5.6. IRQ during IRQ in an example ARMv6system

3.6. ARM7TDMI IRQ interrupts using AHB

3.7. Interrupt priority

4. Programmer’s Model for Test

4.1. PrimeCell VIC test harness overview

4.2. Scan testing

4.3. Test registers

4.3.1. Test Control Register, VICITCR
4.3.2. Integration Test Input Register 1,VICITIP1
4.3.3. Integration Test Input Register 2,VICITIP2
4.3.4. Integration Test Output Register 1,VICITOP1
4.3.5. Integration Test Output Register 2,VICITOP2
4.3.6. Sampled Interrupt Source Status Register,VICINTSSTATUS
4.3.7. Sampled Interrupt Source Status ClearRegister, VICINTSSTATUSCLEAR

A. Signal Descriptions

A.1. AMBA AHB signals
A.2. Interrupt controller signals
A.3. Daisy chain signals
A.4. VIC port signals
A.5. Scan test control signals

B. Example Code

B.1. About the example code

B.1.1. Enable interrupts
B.1.2. Disable interrupts
B.1.3. Interrupt polling
B.1.4. Generate software interrupt
B.1.5. Clear software interrupt
B.1.6. FIQ interrupt initialization
B.1.7. FIQ interrupt handler
B.1.8. Vectored interrupt initialization
B.1.9. Vectored interrupt service routine
B.1.10. Daisy-chained vectored interrupt serviceroutine
B.1.11. Highest level vectored IRQ interruptservice routine

C. Troubleshooting

C.1. Troubleshooting

List of Figures

2.1. VIC block diagram
2.2. Interrupt request logic
2.3. Nonvectored FIQ interrupt logic
2.4. Vectored IRQ interrupt logic
2.5. Interrupt priority logic
2.6. Single interrupt controller connectivity
2.7. Daisy-chained VIC0 blocking mode
2.8. Daisy-chained interrupt controllerconnectivity
2.9. Daisy-chained timing example
2.10. Daisy-chained VIC blocking mode
2.11. VIC port connectivity for synchronousmode
2.12. VIC port timing example, processorand bus clocks synchronous and same frequency
2.13. VIC port timing example, processorclock synchronous and twice bus clock frequency
2.14. VIC port timing example, processorand bus clocks asynchronous
3.1. Peripheral Identification Registerbit assignment
3.2. PrimeCell Identification Registerbit assignment

List of Tables

2.1. Interrupt standard configuration
3.1. PrimeCell VIC register summary
3.2. VICIRQSTATUS Register bit assignments
3.3. VICFIQSTATUS Register bit assignments
3.4. VICRAWINTR Register bit assignments
3.5. VICINTSELECT Register bit assignments
3.6. VICINTENABLE Register bit assignments
3.7. VICINTENCLEAR Register bit assignments
3.8. VICSOFTINT Register bit assignments
3.9. VICSOFTINTCLEAR Register bit assignments
3.10. VICPROTECTION Register bit assignments
3.11. VICADRESS Register bit assignments
3.12. VICSWPRIORITYMASK Register bit assignments
3.13. VICVECTADDR[0-31] Register bit assignments
3.14. VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY Register bitassignments
3.15. VICPERIPHID0 Register bit assignments
3.16. VICPERIPHD1 Register bit assignments
3.17. VICPERIPHID2 Register bit assignments
3.18. VICPERIPHID3 Register bit assignments
3.19. VICPCELLID0 Register bit assignments
3.20. VICPCELLID1 Register bit assignments
3.21. VICPCELLID2 Register bit assignments
3.22. VICPCELLID3 Register bit assignments
3.23. ARM7TDMI FIQ interrupt latency
3.24. ARM966E-S Rev 2 FIQ interrupt latency
3.25. ARM946E-S Rev 1.1 FIQ interrupt latency
3.26. ARM926EJ-S FIQ interrupt latency
3.27. ARM1026EJ-S FIQ interrupt latency
3.28. ARM7TDMI IRQ interrupt latency
4.1. Test registers memory map
4.2. VICITCR Register bit assignments
4.3. VICITIP1 Register bit assignments
4.4. VICITIP2 Register bit assignments
4.5. VICITOP1 Register bit assignments
4.6. VICITOP2 Register bit assignments
4.7. VICINTSSTATUS Register bit assignments
4.8. VICINTSSTATUSCLEAR Register bit assignments
A.1. AMBA AHB signal descriptions
A.2. Interrupt controller signals
A.3. Daisy chain signals
A.4. VIC port signals
A.5. Scan test control signals
C.1. Troubleshooting

Proprietary Notice

ARM, the ARM Powered logo, Thumb, and StrongARM are registeredtrademarks of ARM Limited.

The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ModelGen,Multi-ICE, PrimeCell, ARM7TDMI, ARM7TDMI-S, ARM9TDMI, ARM9E-S, ARM966E-S,ETM7, ETM9, TDMI and STRONG are trademarks of ARM Limited.

All other products or services mentioned herein may be trademarksof their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A	December2002	First issue.

Copyright © 2002 ARM Limited. All rights reserved.	ARM DDI 0273A
Non-Confidential
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