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| Home > Programmer’s Model > VFP11 system registers > Floating Point Instruction Registers, FPINST and FPINST2 |
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The VFP11 coprocessor has two instruction registers:
The FPINST register contains the exceptional instruction.
The FPINST2 register contains the instruction that was issued to the VFP11 coprocessor before the exception was detected. This instruction was retired in the ARM1136 processor and cannot be reissued. It must be executed by support code.
The FPINST and FPINST2 are accessible only in privileged modes.
The instruction in the FPINST register is in the same format as the issued instruction but is modified in several ways. The condition code flags, FPINST[31:28], are forced to b1110, the AL (always) condition. If the instruction is a short vector, the source and destination registers that reference vectors are updated to point to the source and destination registers of the exceptional iteration. See Exception processing for CDP short vector instructions for more information.
The instruction in the FPINST2 register is in the same format as the issued instruction but is modified by forcing the condition code flags, FPINST2[31:28] to b1110, the AL (always) condition.
| Copyright © 2002, 2003, 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0274H |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > VFP11 system registers > Floating Point Instruction Registers, FPINST and FPINST2 |