VFP11™ Vector Floating-point Coprocessor Technical Reference Manual 3.4.5. Media and VFP Feature Registers

3.4.5. Media and VFP Feature Registers

The purpose of the Media and VFP Feature Registers is to provide information about the features that the VFP unit contains.

The Media and VFP Feature Registers:

are two 32-bit read-only registers
when the VFP is enabled by the EN bit in the Floating Point Exception Register, are accessible in any mode
when the VFP is disabled by the EN bit, are accessible only in Privileged mode.

See Floating-Point Exception Register, FPEXC for more information about the EN bit.

Media and VFP Feature Register 0

Figure 3.8 shows the Media and VFP Feature Register 0 bit fields.

This register is first implemented in the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.8. Media and VFP Feature Register 0

The values in the Media and VFP Feature Register 0 are implementation defined. Table 3.9 describes the Media and VFP Feature Register 0 bit fields for the VFP11 coprocessor.

Table 3.9. Media and VFP Feature Register 0 bit fields

Bit range	Field name	Function
[31:28]	-	Indicates the VFP hardware support level when user traps are disabled. `0x1`, in VFP11 coprocessors when Flush-to-Zero and Default_NaN and Round-to-Nearest are all selected in FPSCR, the coprocessor does not require support code. Otherwise floating point support code is required.
[27:24]	-	Indicates support for short vectors. `0x1`, VFP11 coprocessors support short vectors.
[23:20]	-	Indicates support for hardware square root. `0x1`, VFP11 coprocessors support hardware square root.
[19:16]	-	Indicates support for hardware divide. `0x1`, VFP11 coprocessors support hardware divide.
[15:12]	-	Indicates support for user traps. `0x1`, VFP11 coprocessors support software traps, support code is required.
[11:8]	-	Indicates support for double precision VFP. `0x1`, VFP11 coprocessors support v2.
[7:4]	-	Indicates support for single precision VFP. `0x1`, VFP11 coprocessors support v2.
[3:0]	-	Indicates support for the media register bank. `0x1`, VFP11 coprocessors support 16, 64-bit registers.

Media and VFP Feature Register 1

Figure 3.9 shows the Media and VFP Feature Register 1 bit fields.

This register is first implemented in the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.9. Media and VFP Feature Register 1

The values in the Media and VFP Feature Register 1 are implementation defined. Table 3.10 describes the Media and VFP Feature Register 0 bit fields for the VFP11 coprocessor.

Table 3.10. Media and VFP Feature Register 1 bit fields

Bit range	Field name	Function
[31:12]	-	Reserved. Read as zero.
[11:8]	-	Indicates support for media extension, single precision floating point instructions. `0x0`, no support in VFP11 coprocessors.
[7:4]	-	Indicates support for media extension, integer instructions. `0x0`, no support in VFP11 coprocessors.
[3:0]	-	Indicates support for media extension, load/store instructions. `0x0`, no support in VFP11 coprocessors.

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