The interface between the ARM1136JF-S processor and the VFP11 coprocessor specifies that an exceptional instruction that bounces to support code must signal on a subsequent coprocessor instruction. This is known as imprecise exception handling. It means that when the exception is processed, the VFP11 and ARM1136 user states might be different from their states when the exceptional instruction executed. Parallel execution of VFP11 CDP instructions and data transfer instructions means that the VFP11 and ARM1136 register files and memory might be modified outside the program order.