In Example 4.12, a short vector divide is followed by a FADDS instruction. The short vector divide has b001 in the LEN field, selecting a vector length of two iterations. It requires the Execute 1 stage of the FMAC pipeline for the first cycle of each iteration of the divide, resulting in a stall of the FADDS until the final iteration of the divide completes the first Execute 1 cycle. The divide iterates for 14 cycles in the Execute 1 and Execute 2 stages of the DS pipeline, shown in Table 4.14 as E1. The first and shared Execute 1 cycle for each divide iteration is designated as E1’.

FDIVS S8, S10, S12

FADDS S0, S0, S1

Table 4.14 and Table 4.15 show the pipeline stages for Example 4.12.