If the coprocessor is not in RunFast mode, it detects Underflow pessimistically. If the support code confirms the potential underflow for an operation with a floating-point result, it generates an underflow exception. How this is confirmed depends on whether the VFP11 coprocessor is in flush-to-zero mode.

If the FZ bit is set to 1, all underflowing results are forced to a positive signed zero and written to the destination register. The UFC flag is set to 1 in the FPSCR. No trap is taken. If the Underflow exception enable bit is set to 1, it is ignored.

If the FZ bit is not set to 1 what happens next depends on whether the Underflow exception is enabled.