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The VFP11 coprocessor is an implementation of the ARM Vector Floating-point Architecture, VFPv2. It provides low-cost floating-point computation that is compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, referred to in this document as the IEEE 754 standard. The VFP11 coprocessor supports all VFP addressing modes described in the ARM Architecture Reference Manual.
The VFP11 coprocessor is optimized for:
high data transfer bandwidth, using 64-bit split load and store buses
fast hardware execution of a high percentage of VFP operations on normalized data, resulting in higher overall performance while providing full IEEE 754 standard support when required
hardware divide and square root operations in parallel with other arithmetic operations, to reduce the impact of long-latency operations
near IEEE 754 standard compatibility in RunFast mode without support code assistance, providing determinable run-time calculations for all input data
low power consumption, small die size, and reduced kernel code.
The VFP11 coprocessor is an ARM enhanced numeric coprocessor that provides compatibility with the IEEE 754 standard. The VFP11 coprocessor supports single-precision and double-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between floating-point data formats and ARM integer word format, with special operations to perform the conversion in round-towards-zero mode for high-level language support.
The VFP11 coprocessor provides an optimized performance-power-area solution for embedded applications and high performance for general-purpose applications.
This manual describes only VFP11-specific implementation issues. See also the VFP descriptions in the ARM Architecture Reference Manual.
This manual only describes the implementation of the VFP11 for the ARM1136JF-S processor. See Product revisions for information about other implementations of the VFP11.