In Example 5.1, the FMULD instruction is a short vector operation with b011 in the LEN field for a length of four iterations and b00 in the STRIDE field for a vector stride of one. A potential Underflow exception is detected on the third iteration.

FMULD D8, D12, D8       ; Short vector double-precision multiply of length 4

FLDD  D0, [R5]          ; Load of 1 double-precision register

FSTMS R3, {S2-S9}       ; Store multiple of 8 single-precision registers

FLDS  S8, [R9]          ; Load of 1 single-precision register

A double-precision multiply requires two cycles in the Execute 2 stage. The exception on the third iteration is detected in cycle 8. Before the FMULD exception is detected, the FLDD enters the Decode stage in cycle 2, and the FSTMS enters the Decode stage in cycle 3. The FLDD and the FSTMS complete execution and retire. The FLDS stalls in the Decode stage due to a resource conflict with the FSTMS and is the trigger instruction. It is bounced in cycle 9 and can be retried after exception processing. FPINST2 is invalid, and the FP2V flag, FPEXC[28], is not set to 1.

Table 5.1 shows the pipeline stages for Example 5.1.

After exception processing begins, the FPEXC register fields contain the following:

EX        1        The VFP11 coprocessor is in the exceptional state.

EN        1

FP2V      0        FPINST2 does not contain a valid instruction.

VECITR    000      One iteration remains after the exceptional iteration.

INV       0    

UFC       1        Exception detected is a potential underflow.

OFC       0    

IOC       0    

The FPINST register contains the FMULD instruction with the following fields modified to reflect the register address of the third iteration.

Fd/D        1010/0        Destination of the third exceptional iteration is D10.

Fm/M        1010/0        Fm source of the third exceptional iteration is D10.

Fn/N        1110/0        Fn source of the third exceptional iteration is D14.

The FPINST2 register contains invalid data.

In Example 5.2, the first FADDS is a short vector operation with b001 in the LEN field for a vector length of two iterations and b00 in the STRIDE field for a vector stride of one. A potential Invalid Operation exception is detected in the second iteration. The second FADDS progresses to the Execute 1 stage and is captured in the FPINST2 register with the condition field changed to AL, the FP2V flag set to 1, and is not the trigger instruction. The FMULS is the trigger instruction and bounces in cycle 6. It can be retried after exception processing.

FADDS S24, S26, S28        ; Vector single-precision add of length 2

FADDS S3, S4, S5           ; Scalar single-precision add

FMULS S12, S16, S16        ; Short vector single-precision multiply

Table 5.2 shows the pipeline stages for Example 5.2.

After exception processing begins, the FPEXC register fields contains the following:

EX        1        The VFP11 coprocessor is in the exceptional state.

EN        1

FP2V      1        FPINST2 contains a valid instruction.

VECITR    111      No iterations remaining after exceptional iteration.

INV       0

UFC       0

OFC       0

IOC       1        Exception detected is a potential invalid operation.

The FPINST register contains the FADDS instruction with the following fields modified to reflect the register address of the second iteration:

Fd/D      1100/1      Destination is of the second exceptional iteration is S25.

Fn/N      1101/1      Fn source is of the second exceptional iteration is S27.

Fm/M      1110/1      Fm source is of the second exceptional iteration is S29.

The FPINST2 register contains the instruction word for the second FADDS with the condition field changed to AL.

In Example 5.3, FADDD is a short vector instruction with b011 in the LEN field for a vector length of four iterations and b00 in the STRIDE field for a vector stride of one. It has a potential Overflow exception in the first iteration, detected in cycle 4. The following FMACS is stalled in the Decode stage. The FMACS is the trigger instruction and can be retried after exception processing. FPINST2 is invalid and the FP2V flag is not set.

FADDD D4, D4, D12              ; Short vector double-precision add of length 4

FMACS S0, S3, S2               ; Scalar single-precision mac

Table 5.3 shows the pipeline stages for Example 5.3.

After exception processing begins, the FPEXC register fields contain the following:

EX        1        The VFP11 coprocessor is in the exceptional state.

EN        1

FP2V      0        FPINST2 does not contain a valid instruction.

VECITR    010      Three iterations remain.

INV       0

UFC       0

OFC       1        Exception detected is a potential overflow.

IOC       0

The FPINST register contains the FADDD instruction with the following fields modified to reflect the register address of the first iteration:

Fd/D      0100/0        Destination of exceptional iteration is D4.

Fn/N      0100/0        Fn source of the first exceptional iteration is D4.

Fm/M      1100/0        Fm source of the first exceptional iteration is D12.

FPINST2 contains invalid data.