Figure 2.4 shows how the register file is divided into four banks, with eight registers in each bank for single-precision instructions and four registers per bank for double-precision instructions. CDP instructions access the banks in a circular manner. Load and store multiple instructions do not access the registers in a circular manner but treat the register file as a linearly-ordered structure.

See the ARM Architecture Reference Manual for more information about VFP addressing.

A short vector CDP operation that has a source or destination vector crossing a bank boundary wraps around and accesses the first register in the bank.

Example 2.1 shows the iterations of the following short vector add instruction:

FADDS S11, S22, S31

In this instruction, the LEN field contains b101, selecting a vector length of six iterations, and the STRIDE field contains b00, selecting a vector stride of one.

FADDS S11, S22, S31         ; 1st iteration 

FADDS S12, S23, S24         ; 2nd iteration. The 2nd source vector wraps around

                            ; and accesses the 1st register in the 4th bank

FADDS S13, S16, S25         ; 3rd iteration. The 1st source vector wraps around

                            ; and accesses the 1st register in the 3rd bank

FADDS S14, S17, S26         ; 4th iteration

FADDS S15, S18, S27         ; 5th iteration

FADDS S8, S19, S28          ; 6th and last iteration. The destination vector

                            ; wraps around and writes to the 1st register in the

                            ; 2nd bank