An instruction is a scalar-only operation if the operands are treated as scalars and the result is a scalar.

Clearing the LEN field in the FPSCR register to zero selects a vector length of one iteration. For example, if the LEN field contains b000, then the following operation writes the sum of the single-precision values in S21 and S22 to S12:

FADDS S12, S21, S22

Some instructions can operate only on scalar data regardless of the value in the LEN field. These instructions are:

Vector-only instructions require that the value in the LEN field is nonzero, and that the destination and Fm registers are not in bank 0.

Example 2.2 shows the iterations of the following short vector instruction:

FMACS S16, S0, S8

In the example, the LEN field contains b011, selecting a vector length of four iterations, and the STRIDE field contains b00, selecting a vector stride of one.

FMACS S16, S0, S8            ; 1st iteration

FMACS S17, S1, S9            ; 2nd iteration

FMACS S18, S2, S10           ; 3rd iteration

FMACS S19, S3, S11           ; 4th and last iteration

In the VFPv2 architecture, a scalar operand can operate on a vector. The destination must be a vector, that is, not in bank 0, and the Fm operand must be in bank 0.

Example 2.3 shows the iterations of the following short vector instruction with a scalar source:

FMULD D12, D8, D2

In the example, the LEN field contains b001, selecting a vector length of two iterations, and the STRIDE field contains b00, selecting a vector stride of one.

FMULD D12, D8, D2            ; 1st iteration

FMULD D13, D9, D2            ; 2nd and last iteration

This scales the two source registers, D8 and D9, by the value in D2 and writes the new values to D12 and D13.

You can mix scalar and short vector operations by carefully selecting the source and destination registers. If the destination is in bank 0, the operation is scalar-only regardless of the value in the LEN field. You do not have to change the LEN field from a nonzero value to b000 to perform scalar operations.

Example 2.4 shows the sequence of operations for the following instructions:

FABSD D4, D8

FADDS S0, S0, S31

FMULS S24, S26, S1

In the example, the LEN field contains b001, selecting a vector length of two iterations, and the STRIDE field contains b00, selecting a vector stride of one.

FABSD D4, D8          ; vector DP ABS operation on regs (D8, D9) to (D4, D5)

FABSD D5, D9

FADDS S0, S0, S31     ; scalar increment of S0 by S31

FMULS S24, S26, S1    ; vector (S26, S27) scaled by S1 and written to (S24, S25)

FMULS S25, S27, S1

Table 2.7 to Table 2.10 show the four types of operations possible in the VFPv2 architecture. In the tables:

Table 2.7 describes single-precision three-operand register usage.

Table 2.8 describes single-precision two-operand register usage.

Table 2.9 describes double-precision three-operand register usage.

Table 2.10 describes double-precision two-operand register usage.