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The issue timing of VFP11 instructions affects the determination of the trigger instruction. The last iteration of a short vector CDP can be followed in the next cycle by a second CDP instruction. If there is no hazard, the VFP11 coprocessor accepts the second CDP instruction before the exception status of the last iteration of the short vector CDP is known. The second CDP instruction is said to be in the pretrigger slot and is retained in the FPINST2 register for the support code.
The following rules determine which instruction is the trigger instruction:
The first nonserializing instruction after the exceptional condition has been detected is a trigger instruction.
An instruction that accesses the FPSCR register in any processor mode is a trigger instruction.
An instruction that accesses the FPEXC, FPINST, or FPINST2 register in a privileged mode is not a trigger instruction.
An instruction that accesses the FPSID register in any mode is not a trigger instruction.
A data processing instruction that reaches the LS pipeline Execute stage or a CDP instruction that reaches the FMAC or DS pipeline E1 stage is not the trigger instruction. There can be several of these if the exceptional instruction is a sufficiently long short vector instruction, and the exception is detected on a later iteration.
| Copyright © 2002, 2003, 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0274H |
| Non-Confidential | |
| PDF version | |
| Home > Exception Handling > Exception processing > Determination of the trigger instruction |