| Copyright © 2002, 2003 ARM Limited. All rights reserved. | ARM DDI 0275D |
| Non-Confidential | |
 PDF version | |
| Home > Functional Description > Clocks, and resets > Clocks |
| |||
| Home > Functional Description > Clocks, and resets > Clocks | |||
The ETB11 has three clock domains:
TAP controller, clocked by DBGTCK
memory-mapped peripheral, clocked by HCLK
remainder of the system including ETB11 registers, clocked by CLK.
DBGTCK is synchronous to CLK when used with ETM11RV. Synchronization issues can therefore be ignored and are not discussed further. See ETM versions and variants for details of other ETB products,
HCLK can be synchronous or asynchronous to CLK depending on your system design. Synchronization logic is provided for asynchronous designs. Register read and write accesses, and RAM read and write accesses, using the AHB interface are described in:
| Copyright © 2002, 2003 ARM Limited. All rights reserved. | ARM DDI 0275D |
| Non-Confidential | |
| PDF version | |
| Home > Functional Description > Clocks, and resets > Clocks |