ETB11 ™ Technical ReferenceManual

Revision: r0p1

Table of Contents

About this document
Product revision status
Intended audience
Using this manual
Further reading
Feedback on the ETB11
Feedback on this document
1. Introduction
1.1. About the Embedded Trace Buffer
1.2. ETM versions and variants
1.3. Silicon revision
2. Functional Description
2.1. Functional information
2.1.1. Interfaces
2.1.2. Global configurability
2.2. Operation
2.3. Control logic
2.4. Data Formatter
2.5. Trigger delay counter
2.6. Address generation
2.6.1. Write address generation
2.6.2. Read address generation
2.7. BIST interface
2.8. TAP controller
2.8.1. Test data registers
2.8.2. Instruction Register
2.8.3. Asynchronous clocks and testing in ETB11
2.9. Trace RAM interface
2.9.1. Signals
2.9.2. Read access
2.9.3. Write access
2.10. Clocks, and resets
2.10.1. Clocks
2.10.2. Resets
2.11. AHB transfers
2.11.1. Read transfer
2.11.2. Write transfer
3. Programmer’s Model
3.1. About the programmer’s model
3.1.1. Register fields
3.1.2. Register map
3.2. Register descriptions
3.2.1. Identification Register, r0
3.2.2. RAM Depth Register, r1
3.2.3. RAM Width Register, r2
3.2.4. Status Register, r3
3.2.5. RAM Data Register, r4
3.2.6. RAM Read Pointer Register, r5
3.2.7. RAM Write Pointer Register, r6
3.2.8. Trigger Counter Register, r7
3.2.9. Control Register, r8
3.3. Software access to the ETB11 usingthe AHB interface
3.3.1. Restrictions on use of the AHB interface
4. Timing Requirements
4.1. AHB interface
4.2. CLK domain
4.3. IEEE1149.1 interface
A. Signal Descriptions
A.1. Signal properties and requirements
A.2. Signal descriptions
B. Integrating the ETB11
B.1. ASIC connections
B.2. Connecting to ETM11RV
B.3. Connecting the ETB11 in a 64-bit AHBsystem

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The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.


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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A December2002 First release
Revision B February2003 ETB revision has changed to r0p1
Revision C May2003 Description of ETMv1/ETMv2 supported removed.
Revision D August2003 Preface and Index updated and corrected, Resetscorrectly described 2.10.2, and 3.2.5 RAM Data Register corrected.
Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D