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The two-bit read-only MPMCStatus Register provides MPMC status information. This register can be accessed with zero wait states. Table 3.3 lists the bit assignments for the MPMCStatus Register.
Table 3.3. MPMCStatus Register bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:3] | - | Reserved, read undefined. |
| [2] | SA | Self-refresh acknowledge, MPMCSREFACK. This read-only bit indicates the operating mode of the dynamic memory controller: 0 = normal mode 1 = self-refresh mode (reset value on nPOR). |
| [1] | - | Reserved, read undefined. |
| [0] | B | Busy, this read-only bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not: 0 = MPMC is idle 1 = MPMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (reset value on nPOR and HRESETn). |
| Copyright © 2003-2005 ARM Limited. All rights reserved. | ARM DDI 0277F |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Register descriptions > Status Register, MPMCStatus |