MultiPort Memory Controller (GX175) Technical Reference Manual A.2. AHB memory signals

A.2. AHB memory signals

Table A.2 lists the AHB memory signals. The signal names for each port can be found by substituting the port number, 0, 1, 2, 3, or 4 for the symbol x. Unused ports are disabled by connecting their inputs to logic 0. The MPMC does not support RETRY or SPLIT transactions.

Table A.2. AHB memory signal descriptions

Name	Type	Source/ destination	Description
HADDRx[28:0]	Input	AHB master layer	The AHB address bus.
HBURSTx[2:0]	Input	AHB master layer	Burst type. Indicates if the transfer forms part of a burst. 4, 8, and 16 beat bursts are supported and the burst can be either incrementing or wrapping.
HMASTLOCKx	Input	AHB master layer	Locked transfers. When HIGH this signal indicates that the master requires locked access to the SDRAM and no other master must be granted the bus until this signal is LOW.
HPROTx[3:2]	Input	AHB master	The protection control signals provide additional information about a bus access. The signals indicate if the transfer is: an opcode fetch or a data access a privileged mode access or a User mode access a cacheable access or a noncacheable access a bufferable access or a nonbufferable access.
HRDATAx[31:0]	Output	AHB master layer	Read data bus. The read data bus is used to transfer data from the MPMC to the bus master during read operations.
HREADYINx	Input	AHB slave layer	Transfer done. When HIGH, the HREADYINx signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer. An alternate slave generates this signal.
HREADYOUTx	Output	AHB master layer AHB slave layer	Transfer done. When HIGH, the HREADYOUTx signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.
HRESPx[1:0]	Output	AHB master layer	Transfer response. The transfer response provides additional information on the status of a transfer. Four different responses are provided, OKAY, ERROR, RETRY, and SPLIT. The SDRAM controller can respond with either the OKAY or ERROR responses. The ERROR response is generated when: the transfer size is greater than allowed the memory access is a write to a write-protected region the memory is accessed with the MPMC enable (E) bit disabled or the low-power mode (L) bit asserted. See Table 3.2.
HSELMPMCxCS[7:0]	Input	AHB decoder	Slave select. MPMC select signal. These signals indicate an access to memory. Specific chip select, HSELMPMCxCS[0] indicates the transfer is to chip select 0, HSELMPMCxCS[1] indicates the transfer is to chip select 1, and so on. Only one signal can go active at a time. The HSELMPMCxCS to chip select decoding is as follows: HSELMPMCxCS[0] selects nMPMCSTCSOUT[0] HSELMPMCxCS[1] selects nMPMCSTCSOUT[1] HSELMPMCxCS[2] selects nMPMCSTCSOUT[2] HSELMPMCxCS[3] selects nMPMCSTCSOUT[3] HSELMPMCxCS[4] selects nMPMCDYCSOUT[0] HSELMPMCxCS[5] selects nMPMCDYCSOUT[1] HSELMPMCxCS[6] selects nMPMCDYCSOUT[2] HSELMPMCxCS[7] selects nMPMCDYCSOUT[3].
HSELMPMCxG	Input	AHB decoder	Slave select. MPMC global select signal. This signal must go active with the HSELMPMCxCS[7:0] signals, and whenever the MPMC is accessed.
HSIZEx[2:0]	Input	AHB master layer	Transfer size. Indicates the size of the transfer, which is typically byte (8-bit), halfword (16-bit), or word (32-bit). Byte (8-bit), halfword (16-bit), and word (32-bit) transfers are allowed to access the external memory. Transfer sizes greater than 32 bits generate an ERROR response.
HTRANSx[1:0]	Input	AHB master layer	Transfer type. Indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY.
HWDATAx[31:0]	Input	AHB master layer	Write data bus. The write data bus is used to transfer data from the master to the bus slaves during write operations.
HWRITEx	Input	AHB master layer	Transfer direction. When HIGH this signal indicates a write transfer and when LOW a read transfer.

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