MultiPort Memory Controller (GX175) Technical Reference Manual 2.1.2. AHB slave memory interfaces

2.1.2. AHB slave memory interfaces

The AHB slave memory interfaces enable devices to access the external memories. The memory interfaces are prioritized, with interface 0 having the highest priority. Having more than one memory interface gives high-bandwidth peripherals direct access to the MPMC, without data having to pass over the main system bus.

Note

All AHB burst types are supported to enable the most efficient use of memory bandwidth.
The AHB interfaces do not generate SPLIT and RETRY responses.

Memory transaction endianness

The endianness of the data transfers to and from the external memories is determined by the Endian mode (N) bit in the MPMCConfig register.

Note

The memory controller must be idle, see Status Register, MPMCStatus, before endianness is changed, so that the data is transferred correctly.

Memory transaction size

Memory transactions can be 8, 16, or 32 bits wide. Any access attempted with a size greater than a word (32 bits) causes an ERROR response on HRESP and the transfer is terminated.

Write-protected memory areas

Write transactions to write-protected memory areas generate an ERROR response on HRESP and the transfer is terminated.

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