MultiPort Memory Controller (GX175) Technical Reference Manual 2.1. MPMC functional description

2.1. MPMC functional description

The multiport memory controller block optimizes and controls external memory transactions. Figure 2.1 shows a block diagram of the MPMC.

Figure 2.1. MPMC block diagram

Note

In Figure 2.1, the letter x used in the AHB slave memory interface signals denotes a number between 0 and 4.

The functions of the MPMC blocks are described in the following sections:

AHB slave register interface
AHB slave memory interfaces
MBX Interface Port
Data buffers
Arbiter
Memory controller state machine
Pad interface
Test Interface Controller (TIC).

Note

For 32-bit wide chip selects, data is transferred to and from dynamic memory in single SDRAM bursts. For 16-bit wide chip selects, SDRAM bursts of two are used.

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