3.2. Register summary

The MPMC (GX175) registers are summarized in Table 3.1.

Table 3.1. MPMC register summary

Register

Offset

Type

Reset

HRESETn

Reset

nPOR

Description

MPMCControl

0x000

RW

0x1

0x1See Control Register, MPMCControl

MPMCStatus

0x004

RO-0x5See Status Register, MPMCStatus

MPMCConfig

0x008

RW

-

0x-[1]See Configuration Register, MPMCConfig

MPMCDynamicControl

0x020

RW

-

0xE

See Dynamic Memory Control Register, MPMCDynamicControl

MPMCDynamicRefresh

0x024

RW

-

0x0

See Dynamic Memory Refresh Timer Register, MPMCDynamicRefresh

MPMCDynamicReadConfig0x028

RW

-0x----[1]

See Dynamic Memory Read Configuration Register, MPMCDynamicReadConfig

MPMCDynamictRP

0x030

RW

-

0xF

See Dynamic Memory Precharge Command Period Register, MPMCDynamictRP

MPMCDynamictRAS

0x034

RW

-

0xF

See Dynamic Memory Active To Precharge Command Period Register, MPMCDynamictRAS

MPMCDynamictSREX

0x038

RW

-

0x7F

See Dynamic Memory Self-refresh Exit Time Register, MPMCDynamictSREX

MPMCDynamictWR

0x044

RW

-

0xF

See Dynamic Memory Write Recovery Time Register, MPMCDynamictWR

MPMCDynamictRC

0x048

RW

-

0x1F

See Dynamic Memory Active To Active Command Period Register, MPMCDynamictRC

MPMCDynamictRFC

0x04C

RW

-

0x1F

See Dynamic Memory Auto-refresh Period Register, MPMCDynamictRFC

MPMCDynamictXSR

0x050

RW

-

0xFF

See Dynamic Memory Exit Self-refresh Register, MPMCDynamictXSR register

MPMCDynamictRRD

0x054

RW

-

0xF

See Dynamic Memory Active Bank A To Active Bank B Time Register, MPMCDynamictRRD

MPMCDynamictMRD

0x058

RW

-

0xF

See Dynamic Memory Load Mode Register, MPMCDynamictMRD register

MPMCDynamictCDLR

0x05C

RW

-0xF

See Dynamic Memory Last Data In To Read Command Time Register, MPMCDynamictCDLR

MPMCStaticExtendedWait

0x080

RW

-

0x0

See Static Memory Extended Wait Register, MPMCStaticExtendedWait

MPMCDynamicConfig0

0x100

RW

-

0x0

See Dynamic Memory Configuration Registers 0-3, MPMCDynamicConfig0-3

MPMCDynamicRasCas0

0x104

RW

-

0x783

See Dynamic Memory RAS and CAS Delay Registers 0-3, MPMCDynamicRasCas0-3

MPMCDynamicConfig1

0x120

RW

-

0x0--[1]

See Dynamic Memory Configuration Registers 0-3, MPMCDynamicConfig0-3

MPMCDynamicRasCas1

0x124

RW

-

0x--3[1]

See Dynamic Memory RAS and CAS Delay Registers 0-3, MPMCDynamicRasCas0-3

MPMCDynamicConfig2

0x140

RW

-

0x0

See Dynamic Memory Configuration Registers 0-3, MPMCDynamicConfig0-3

MPMCDynamicRasCas2

0x144

RW

-

0x783

See Dynamic Memory RAS and CAS Delay Registers 0-3, MPMCDynamicRasCas0-3

MPMCDynamicConfig3

0x160

RW

-

0x0

See Dynamic Memory Configuration Registers 0-3, MPMCDynamicConfig0-3

MPMCDynamicRasCas3

0x164

RW

-

0x783

See Dynamic Memory RAS and CAS Delay Registers 0-3, MPMCDynamicRasCas0-3

MPMCStaticConfig0

0x200

RW

-

0x-0[1]

See Static Memory Configuration Registers 0-3, MPMCStaticConfig0-3

MPMCStaticWaitWen0

0x204

RW

-

0x0

See Static Memory Write Enable Delay Registers 0-3, MPMCStaticWaitWen0-3

MPMCStaticWaitOen0

0x208

RW

-

0x0

See Static Memory Output Enable Delay Registers 0-3, MPMCStaticWaitOen0-3

MPMCStaticWaitRd0

0x20C

RW

-

0x1F

See Static Memory Read Delay Registers 0-3, MPMCStaticWaitRd0-3

MPMCStaticWaitPage0

0x210

RW

-

0x1F

See Static Memory Page Mode Read Delay Registers 0-3, MPMCStaticWaitPage0-3

MPMCStaticWaitWr0

0x214

RW

-

0x1F

See Static Memory Write Delay Registers 0-3, MPMCStaticWaitWr0-3

MPMCStaticWaitTurn0

0x218

RW

-

0xF

See Static Memory Turn Round Delay Registers 0-3, MPMCStaticWaitTurn0-3

MPMCStaticConfig1

0x220

RW

-

0x--[1]

See Static Memory Configuration Registers 0-3, MPMCStaticConfig0-3

MPMCStaticWaitWen1

0x224

RW

-

0x0

See Static Memory Write Enable Delay Registers 0-3, MPMCStaticWaitWen0-3

MPMCStaticWaitOen1

0x228

RW

-

0x0

See Static Memory Output Enable Delay Registers 0-3, MPMCStaticWaitOen0-3

MPMCStaticWaitRd1

0x22C

RW

-

0x1F

See Static Memory Read Delay Registers 0-3, MPMCStaticWaitRd0-3

MPMCStaticWaitPage1

0x230

RW

-

0x1F

See Static Memory Page Mode Read Delay Registers 0-3, MPMCStaticWaitPage0-3

MPMCStaticWaitWr1

0x234

RW

-

0x1F

See Static Memory Write Delay Registers 0-3, MPMCStaticWaitWr0-3

MPMCStaticWaitTurn1

0x238

RW

-

0xF

See Static Memory Turn Round Delay Registers 0-3, MPMCStaticWaitTurn0-3

MPMCStaticConfig2

0x240

RW

-

0x-0[1]

See Static Memory Configuration Registers 0-3, MPMCStaticConfig0-3

MPMCStaticWaitWen2

0x244

RW

-

0x0

See Static Memory Write Enable Delay Registers 0-3, MPMCStaticWaitWen0-3

MPMCStaticWaitOen2

0x248

RW

-

0x0

See Static Memory Output Enable Delay Registers 0-3, MPMCStaticWaitOen0-3

MPMCStaticWaitRd2

0x24C

RW

-

0x1F

See Static Memory Read Delay Registers 0-3, MPMCStaticWaitRd0-3

MPMCStaticWaitPage2

0x250

RW

-

0x1F

See Static Memory Page Mode Read Delay Registers 0-3, MPMCStaticWaitPage0-3

MPMCStaticWaitWr2

0x254

RW

-

0x1F

See Static Memory Write Delay Registers 0-3, MPMCStaticWaitWr0-3

MPMCStaticWaitTurn2

0x258

RW

-

0xF

See Static Memory Turn Round Delay Registers 0-3, MPMCStaticWaitTurn0-3

MPMCStaticConfig3

0x260

RW

-

0x-0[1]

See Static Memory Configuration Registers 0-3, MPMCStaticConfig0-3

MPMCStaticWaitWen3

0x264

RW

-

0x0

See Static Memory Write Enable Delay Registers 0-3, MPMCStaticWaitWen0-3

MPMCStaticWaitOen3

0x268

RW

-

0x0

See Static Memory Output Enable Delay Registers 0-3, MPMCStaticWaitOen0-3

MPMCStaticWaitRd3

0x26C

RW

-

0x1F

See Static Memory Read Delay Registers 0-3, MPMCStaticWaitRd0-3

MPMCStaticWaitPage3

0x270

RW

-

0x1F

See Static Memory Page Mode Read Delay Registers 0-3, MPMCStaticWaitPage0-3

MPMCStaticWaitWr3

0x274

RW

-

0x1F

See Static Memory Write Delay Registers 0-3, MPMCStaticWaitWr0-3

MPMCStaticWaitTurn3

0x278

RW

-

0xF

See Static Memory Turn Round Delay Registers 0-3, MPMCStaticWaitTurn0-3

MPMCAHBControl0

0x400

RW

-

0x0

See AHB Control Registers 0-4, MPMCAHBControl0-4

MPMCAHBStatus0

0x404

RW

-

0x0See AHB Status Registers 0-4, MPMCAHBStatus0-4

MPMCAHBTimeOut0

0x408

RW

-

0x0

See AHB TimeOut Registers 0-4, MPMCAHBTimeOut0-4

MPMCAHBControl1

0x420

RW

-

0x0

See AHB Control Registers 0-4, MPMCAHBControl0-4

MPMCAHBStatus1

0x424

RW

-

0x0See AHB Status Registers 0-4, MPMCAHBStatus0-4

MPMCAHBTimeOut1

0x428

RW

-

0x0

See AHB TimeOut Registers 0-4, MPMCAHBTimeOut0-4

MPMCAHBControl2

0x440

RW

-

0x0

See AHB Control Registers 0-4, MPMCAHBControl0-4

MPMCAHBStatus2

0x444

RW

-

0x0See AHB Status Registers 0-4, MPMCAHBStatus0-4

MPMCAHBTimeOut2

0x448

RW

-

0x0

See AHB TimeOut Registers 0-4, MPMCAHBTimeOut0-4

MPMCAHBControl3

0x460

RW

-

0x0

See AHB Control Registers 0-4, MPMCAHBControl0-4

MPMCAHBStatus3

0x464

RW

-

0x0See AHB Status Registers 0-4, MPMCAHBStatus0-4

MPMCAHBTimeOut3

0x468

RW

-

0x0

See AHB TimeOut Registers 0-4, MPMCAHBTimeOut0-4

MPMCAHBControl4

0x480

RW

-

0x0

See AHB Control Registers 0-4, MPMCAHBControl0-4

MPMCAHBStatus4

0x484

RW

-

0x0See AHB Status Registers 0-4, MPMCAHBStatus0-4

MPMCAHBTimeOut4

0x488

RW

-

0x0

See AHB TimeOut Registers 0-4, MPMCAHBTimeOut0-4

MPMCITCR

0xF00

RW

0x-[1]

0x-[1]

See Test Control Register, MPMCITCR

MPMCITIP0

0xF20

RW

0x----[1]

0x----[1]

See Test Input 0 Register, MPMCITIP0

MPMCITIP1

0xF24

RW

0x--[1]

0x--[1]

See Test Input 1 Register, MPMCITIP1

MPMCITOP

0xF40

RW

-

0x1[2]

See Test Output Register, MPMCITOP

MPMCPeriphID4

0xFD0

RO

0x5

0x5

See Additional Peripheral Identification Register 4, MPMCPeriphID4

MPMCPeriphID5

0xFD4

RO

0x0

0x0

See Additional Peripheral Identification Registers 5-7, MPMCPeriphID5-7

MPMCPeriphID6

0xFD8

RO

0x0

0x0

See Additional Peripheral Identification Registers 5-7, MPMCPeriphID5-7

MPMCPeriphID7

0xFDC

RO

0x0

0x0

See Additional Peripheral Identification Registers 5-7, MPMCPeriphID5-7

MPMCPeriphID0

0xFE0

RO

0x75

0x75

See Peripheral Identification Register 0, MPMCPeriphID0

MPMCPeriphID1

0xFE4

RO

0x11

0x11

See Peripheral Identification Register 1, MPMCPeriphID1 register

MPMCPeriphID2

0xFE8

RO

0x-4[3]

0x-4[1]

See Peripheral Identification Register 2, MPMCPeriphID2 register

MPMCPeriphID3

0xFEC

RO

0x47

0x47

See Peripheral Identification Register 3, MPMCPeriphID3 register

MPMCPCellID0

0xFFO

RO

0xD

0xD

See PrimeCell Identification Registers 0-3, MPMCPCellID0-3

MPMCPCellID1

0xFF4

RO

0xF0

0xF0

See PrimeCell Identification Registers 0-3, MPMCPCellID0-3

MPMCPCellID2

0xFF8

RO

0x5

0x5

See PrimeCell Identification Registers 0-3, MPMCPCellID0-3

MPMCPCellID3

0xFFC

RO

0xB1

0xB1

See PrimeCell Identification Registers 0-3, MPMCPCellID0-3

[1] Tie-off dependent.

[2] Reflects MPMCSREFACK that is set on power-on reset.

[3] Revision dependent.

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