MultiPort Memory Controller (GX176) Technical Reference Manual 3.3.31. NAND Memory Timing Value 2 Register

3.3.31. NAND Memory Timing Value 2 Register

The 18-bit, read/write, MPMCNANDTiming1 Register enables you to program the second set of NAND flash timing parameters. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the MPMC is idle, and then entering low-power or disabled mode. Software must poll the NDTX bit in the MPMCNANDStatus Register before programming the timing register. This register is accessed with zero wait states.

Figure 3.31 shows the register bit assignments

Figure 3.31. MPMCNANDTiming2Register bit assignments

Table 3.34 lists the register bit assignments.

Table 3.34. MPMCNANDTiming2Register bit assignments

Bits	Name	Description
[31:25]	-	Read undefined. Write as zero.
[24:20]	NAND CE HIGH hold time at last serial read (t_CEH)	`0x00`-`0x1E` = (n+1) HCLK cycles`0x1F` = 32 HCLK cycles (reset value on nPOR). The worst case value for the parameter t_CEH on all NAND flash devices in the system must be programmed.
[19]	-	Read undefined. Write as zero.
[18:16]	NAND RE HIGH hold time (t_REH)	`0x0`-`0x6` = (n+1) HCLK cycles`0x7` = 8 HCLK cycles (reset value on nPOR). The worst case value for the parameter t_REH on all NAND flash devices in the system must be programmed.
[15:13]	-	Read undefined. Write as zero.
[12:8]	NAND read cycle time (t_RC)	`0x00`-`0x1E` = (n+1) HCLK cycles`0x1F` = 32 HCLK cycles (reset value on nPOR). The worst case value for the parameter t_RC on all NAND flash devices in the system must be programmed.
[7:5]	-	Read undefined. Write as zero.
[4:0]	NAND ready to RE falling edge (t_RR)	`0x00`-`0x1E` = n HCLK cycles`0x1F` = 31 HCLK cycles (reset value on nPOR). The worst case value for the parameter t_RR on all NAND flash devices in the system must be programmed.

Note

No timing value is specified for the read access time t_REA, because this is calculated from the t_RC and t_REH values. For all read transfers, t_REA=t_RC-t_REH. Some devices specify a longer read access time for ID read transfers. For these devices, an increased t_RC value must be programmed for the ID read. It can then be set to the standard read value for all subsequent standard data reads. Some devices might not specify a requirement for the t_CEH parameter. The timing value can be programmed to zero for these devices to reduce the read access time.

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