MultiPort Memory Controller (GX176) Technical Reference Manual 3.3.27. NAND Memory Control Vector Register

3.3.27. NAND Memory Control Vector Register

The 28-bit, read/write, MPMCNANDControl Register enables you to program the NAND flash command vector values, and to set other control values for the NAND flash transfer. The register fields can be altered during normal operation, but it is recommended that they are only modified before a NAND access is initiated. This register is accessed with zero wait states.

Figure 3.27 shows the register bit assignments.

Figure 3.27. MPMCNANDControl Register bit assignments

Table 3.30 lists the bit assignments.

Table 3.30. MPMCNANDControl Register bit assignments

Bits	Name	Description
[31]	Transfer type (NDTXRW)	0 = read transfer (reset value on nPOR) 1 = write transfer. Defines the type of transfer that is performed, either a read, or a write. A transfer that performs a data read must be programmed as a read. A transfer that performs a data write or has no data phase, such as a block erase, must be programmed as a write.
[30:27]	-	Read undefined. Write as zero.
[26]	Short read timing (NDSHORTRD)	0 = standard read transfer (reset value on nPOR) 1 = short read transfer. Identifies when a read transfer is performed without a check for the ready/busy output status. A standard read transfer checks that the device ready/busy output indicates the device is ready before performing the data phase of the transfer. For a short read transfer, the t_CLR timing value is used to time the read transfer delay between the deassertion of the command latch enable, and the assertion of the read enable. Commands such as random page read require this setting because the ready/busy output is not used to control the delay to the data phase. This bit does not have to be set for a Status Read, because this transfer is automatically detected and is performed differently because it does not have an address phase.
[25]	ID read command (NDIDRD)	0 = command is not ID read (reset value on nPOR) 1 = read ID command is performed. Identifies that the transfer being performed is reading the device ID, enabling the correct timing to be applied during the transfer (t_AR1).
[24]	Second command phase (NDCMDPH2)	0 = no second command phase (reset value on nPOR) 1 = second command phase is performed. Controls whether a second command phase is performed at the end of the transfer. Commands such as page program might require a second command phase in the transfer.
[23]	Data phase (NDDATAPH)	0 = no data phase (reset value on nPOR) 1 = data phase is performed. Controls whether a data phase is performed during the transfer. Commands such as block erase might not require a data phase in the transfer.
[22:20]	Address phase (NDADDRPH)	`0x0` = no address phase (reset value on nPOR) `0x1`-`0x5` = n address vectors in address phase `0x6`-`0x7` = reserved. Controls whether an address phase is performed during the transfer, and the number of address vectors in the address phase. Commands such as a status read might not require an address phase in the transfer.
[19:16]	Chip select for transfer (NDCS)	0001 = chip select 0 (reset value on nPOR) 0010 = chip select 1 0100 = chip select 2 1000 = chip select 3. Sets the chip select to use for the NAND access. Only one bit of the register can be valid at a time.
[15:8]	Second command vector (NDCMDV2)	`0x00`-`0xFF` = NAND flash second command vector (reset value on nPOR is `0x00`). See the applicable specification for the NAND device for the commands supported. This field is programmed for each NAND access that is performed. The second command vector is only used if the NDCMDPH2 bit of the MPMCNANDControl Register is set HIGH.
[7:0]	First command vector (NDCMDV1)	`0x00`-`0xFF` = NAND flash first command vector (reset value on nPOR is `0x00`). See the applicable specification for the NAND device for the commands supported. This field is programmed for each NAND access that is performed.

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