| Copyright © 2003 ARM Limited. All rights reserved. | ARM DDI 0278B |
| Non-Confidential | |
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The one-bit, read/write, MPMCConfig Register configures the operation of the memory controller. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the MPMC is idle and then entering low-power or disabled mode. This register is accessed with one wait state. Figure 3.3 shows the register bit assignments.
Table 3.4 lists the register bit assignments..
Table 3.4. MPMCConfig Register bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:1] | - | Read undefined. Write as zero. |
| [0] | Endian mode (N) | Endian mode: 0 = little-endian mode (reset value on nPOR) 1 = big-endian mode. The value of the endian bit on nPOR is determined by MPMCBIGENDIAN. This value can be overridden by software. This field is unaffected by HRESETn.[1][2] |
[1] The value of the MPMCBIGENDIAN signal is not reflected in this field. This field reflects the last value that was written into it. [2] Setting little-endian mode in this register has no effect on 64-bit ports which are hardwired as mixed-endian by tying their MPMCBSTRBENx signal HIGH. Setting big-endian in this register forces all ports to big-endian mode, irrespective of the state of the MPMCBSTBRENx signal. | ||
| Copyright © 2003 ARM Limited. All rights reserved. | ARM DDI 0278B |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Register descriptions > Configuration Register |