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Table A.10 describes the TIC signals.
Table A.10. TIC signal descriptions
| Name | Type | Source/ destination | Description |
|---|---|---|---|
HADDRTIC[31:0] Address bus | Output | AHB slave layer | The 32-bit AHB address bus. |
HBUSREQTIC Bus request | Output | AHB arbiter | A signal from the TIC to the bus arbiter indicates that it requires the bus. |
HBURSTTIC[2:0] Burst type | Output | AHB slave layer | Indicates if the transfer forms part of a burst. The TIC always performs incrementing bursts of unspecified length. |
HGRANTTIC Bus grant | Input | AHB arbiter | This signal indicates that the TIC is currently the highest priority master. Ownership of the address and control signals changes at the end of a transfer when HREADYINTIC is HIGH, so the TIC gains access to the bus when both HREADYINTIC and HGRANTTIC are HIGH. |
HLOCKTIC Locked transfers | Output | AHB arbiter | When HIGH this signal indicates that the TIC requires locked access to the bus. No other master must be granted the bus until this signal is LOW. |
HPROT[3:0] Protection control | Output | AHB slave layer | The protection control signals indicate if the transfer is an opcode fetch or data access, as well as if the transfer is a supervisor mode access or a User mode access. These signals also indicate if the current access is cacheable or bufferable. |
HRDATATIC[31:0] Read databus | Input | AHB master layer | The read databus is used to transfer data from the AHB slave to the TIC during read operations. |
HREADYINTIC Transfer done | Input | AHB slave layer | When HIGH the HREADYINTIC signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer. |
HRESPTIC[1:0] Transfer response | Input | AHB slave layer | The transfer response provides additional information on the status of a transfer. Four different responses are provided, OKAY, ERROR, RETRY, and SPLIT. |
HSIZETIC[2:0] Transfer size | Output | AHB slave layer | Indicates the size of the transfer, which is typically byte (8-bit), halfword (16-bit), or word (32-bit). The TIC does not support larger transfer sizes. |
HTRANSTIC[1:0] Transfer type | Output | AHB slave layer | Indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY. The TIC does not use the BUSY transfer type. |
HWDATATIC[31:0] Write databus | Output | AHB slave layer | The write databus is used to transfer data from the master to the bus slaves during write operations. |
HWRITETIC Transfer direction | Output | AHB slave layer | When HIGH, this signal indicates a write transfer and when LOW a read transfer. |
| Copyright © 2003 ARM Limited. All rights reserved. | ARM DDI 0278B |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > Test Interface Controller (TIC) AHB signals |