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Table A.9 describes the pad interface and control signals.
Table A.9. Pad interface and control signal descriptions
| Name | Type | Source/ destination | Description |
|---|---|---|---|
| MPMCADDROUT[27:0] | Output | Pad | Address output. Used for both static and SDRAM devices. 256Mb maximum per static memory bank. SDRAM uses bits [14:0]. Not used by NAND flash. Auto-precharge connections use the MPMCAPOUT output instead of bits [8] or [10] of MPMCADDROUT. |
| MPMCAPOUT | Output | Pad | SDRAM auto-precharge address bit. Micron SyncFlash and V-SyncFlash active terminate command control bit. |
| MPMCCKEOUT[3:0] | Output | Pad | SDRAM clock enables. Used for SDRAM devices. |
| MPMCCLKOUT[3:0] | Output | Pad | Positive differential clocks. Four clocks provide support for 16-bit minimum width SDRAM devices when using 64-bit wide memory. 8-bit devices are not supported for 64-bit wide memory. |
| MPMCDATAIN[63:0] | Input | Pad | Read data from memory. Used for the static memory controller, the dynamic memory controller and the TIC:MPMCDATAIN[63:32] = Read upper data word for SDRAM.MPMCDATAIN[31:0] = Read lower data word for SDRAM, read upper and lower data word for DDR-SDRAM, read data word for static memory and read data word for TIC. MPMCDATAIN[7:0] = Read databus for NAND flash devices. 16-bit NAND flash devices also use MPMCDATAIN[15:8]. |
| MPMCDATAOUT[63:0] | Output | Pad | Data output to memory. Used for the static memory controller, the dynamic memory controller and the TIC:MPMCDATAOUT[63:32] = Write upper data word for SDRAM.MPMCDATAOUT[31:0] = Write lower data word for SDRAM, write upper and lower data word for DDR-SDRAM, write data word for static memory and write data word for TIC.MPMCDATAOUT[7:0] = Control, address and write databus for NAND flash devices. 16-bit NAND flash devices also use MPMCDATAOUT[15:8] for write data only. |
MPMCDQMOUT[7:0] | Output | Pad | Data mask output to SDRAMs. Used for SDRAM devices:MPMCDQMOUT[7:4] = Data mask output, one per byte, for upper word of SDRAM.MPMCDQMOUT[3:0] = Data mask output, one per byte, for lower word of SDRAM or upper and lower word of DDR-SDRAM. |
MPMCDQSIN[3:0] | Input | Pad | Input data strobes, one per byte, for DDR-SDRAM upper or lower word. |
| MPMCDQSOUT[3:0] | Output | Pad | Output data strobe, one per byte, for DDR-SDRAM upper or lower word. |
| MPMCFBCLKIN[7:0] | Input | Pad | Positive differential fed-back clock. Used for SDRAM devices. |
MPMCNDALEOUT | Output | Pad | NAND flash address latch enable. |
MPMCNDCLEOUT | Output | Pad | NAND flash command latch enable. |
| MPMCNDREADYIN [3:0] | Input | Pad | NAND flash device ready outputs, for all four possible devices. Deasserted LOW to indicate that the device is busy. Unused inputs must be tied HIGH. |
| MPMCRPVHHOUT | Output | Pad | Voltage control for Micro Syncflash reset signal (RP). |
| nMPMCBLSOUT[3:0] | Output | Pad | Byte lane select, active LOW, for static memories. Used for static memory devices. |
| nMPMCCASOUT | Output | Pad | Column address strobe. Used for SDRAM devices. |
| nMPMCCLKOUT[3:0] | Output | Pad | Negative differential clocks. Four clocks provide support for 16-bit minimum width SDRAM devices when using 64-bit wide memory. 8-bit devices are not supported for 64-bit wide memory. |
nMPMCDATAOUTEN [7:0] | Output | Pad | nMPMCDATAOUTEN[7:4] = Tristate I/O pad enable for the external memory databus MPMCDATA[63:32], active LOW. Enables the external memory databus byte lanes [63:56], [55:48], [47:40], and [39:32] independently, for upper output data word for SDRAM. nMPMCDATAOUTEN[3:0] = Tristate I/O pad enable for the external memory databus MPMCDATA[31:0], active LOW. Enables the external memory databus byte lanes [31:24], [23:16], [15:8], and [7:0] independently, for lower output data word for SDRAM, output data word for static memory or TIC, or upper and lower output data word for DDR-SDRAM. The lower 1 or 2 byte lanes are used for NAND flash |
nMPMCDQSIN[3:0] | Input | Pad | Half-cycle delayed input data strobes, one per byte, for DDR-SDRAM upper or lower word. |
| nMPMCDQSOUTEN[3:0] | Output | Pad | Tristate I/O pad enable for the output data strobes, active LOW. Enables the memory device byte lanes [31:24], [23:16], [15:8], and [7:0] for DDR-SDRAM output data strobes independently. |
| nMPMCDYCSOUT[3:0] | Output | Pad | Active LOW chip selects for SDRAM. CS[7:4]. |
| nMPMCDYWEOUT | Output | Pad | Write enable for dynamic memory. |
nMPMCNDREOUT | Output | Pad | Read enable for NAND flash memory. |
nMPMCNDWEOUT | Output | Pad | Write enable for NAND flash memory. |
| nMPMCOEOUT | Output | Pad | Output enable for static memories. Used for static memory devices. |
| nMPMCRASOUT | Output | Pad | Row address strobe. Used for SDRAM devices. |
| nMPMCRPOUT | Output | Pad | Reset power down to SyncFlash memory. Used for the dynamic memory controller. |
| nMPMCSTCSOUT[3:0] | Output | Pad | Default active LOW chip selects for static memory and NAND flash. CS[3:0]. |
| nMPMCSTWEOUT (MPMCTESTACK) | Output | Pad | Write enable for static memory. (Test bus acknowledge signal for TIC test mode.) |
| Copyright © 2003 ARM Limited. All rights reserved. | ARM DDI 0278B |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > Pad interface and control signals |