MultiPort Memory Controller (GX176) Technical Reference Manual 2.1.1. Multiport memory controller block

2.1.1. Multiport memory controller block

The multiport memory controller block optimizes and controls external memory transactions. The block contains the following:

Command sequencer

The command sequencer holds up to 10 requests in its internal buffer. It prioritizes and rearranges accesses to maximize memory bandwidth and minimize transaction latency.

For example, if AHB interfaces 3 and 2 simultaneously request a data transfer from dynamic memory, to different memory banks, and the port 3 request address is to a closed page, but port 2 address is for an already open page, the following sequence occurs:

The ACT command is sent to open the SDRAM row specified by the AHB interface 3 address.
The AHB interface 2 access is completed.
AHB interface 3 access is completed.

The access priority is modified to take into account the ease of getting data to complete each transfer, but the access priority is always biased to the highest priority AHB interface.

Memory transfer state machine

The memory transfer state machine controls memory transactions.

Static memory controller register bank

There are four static memory controller register banks. Each contains the registers for a static memory bank.

Dynamic memory controller register bank

There are four dynamic memory controller register banks. Each contains the registers for a dynamic memory bank.

Note

The dynamic memory controller supports only SINGLE access bursts, that is:

single transfer bursts for 64-bit wide external memory
bursts of two transfers for 32-bit wide external memory
bursts of four transfers for 16-bit wide external memory.

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