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The AHB slave memory interfaces enable devices to access the external memories. The memory interfaces are prioritized, with interface 0 having the highest priority. Having more than one memory interface enables high-bandwidth peripherals direct access to the MPMC, without data having to pass over the main system bus. This reduces memory access latency.
All AHB burst types are supported, enabling the most efficient use of memory bandwidth.
The AHB interfaces do not generate SPLIT and RETRY responses.
AHB masters cannot be made to function on a narrower bus than originally intended, unless there is some mechanism included within the master to limit the width of transfers that the bus master attempts. The MPMC is designed to provide a selected mix of 32-bit and 64-bit AHB interfaces on a port-by-port basis. The required port mix can be configured as required for the application, either by adding or removing 32-bit or 64-bit ports, or by changing the order and priority of the port instantiations. If it is necessary to connect a 32-bit AHB master to one of the 64-bit AHB memory slave interfaces, an external conditioning block, similar to that shown in Figure 2.3, is required.
If a 32-bit master is required on a high priority port, it is more efficient to replace a 64-bit port with a 32-bit port, rather than adding external logic to enable the 32-bit master to interface to a 64-bit port.
The following rules are applicable when handling memory transactions in the MPMC:
If the global MPMCBIGENDIAN signal is LOW, all 32-bit AHB ports are fixed as little-endian.
If the global MPMCBIGENDIAN signal is HIGH, all 32-bit AHB ports are fixed as big-endian.
If the global MPMCBIGENDIAN signal is LOW and the MPMCBSTRBENx signal of a port is LOW, that port is fixed as little-endian.
If the global MPMCBIGENDIAN signal is LOW and the MPMCBSTRBENx signal of a port is HIGH, that port is fixed as mixed-endian.
If the global MPMCBIGENDIAN signal is HIGH, all ports are fixed as big-endian irrespective of the state of their MPMCBSTRBENx signal.
If the global MPMCBIGENDIAN signal is LOW, all external memory banks are fixed as little-endian.
If the global MPMCBIGENDIAN signal is HIGH, all external memory banks are fixed as big-endian.
Table 2.1 shows a truth table for the MPMC endianness conditions.
Table 2.1. MPMC endianness options
| MPMCBIGENDIAN | MPMCBSTRBENx | 64-bit AHB port | 32-bit AHB port | External memory bank |
|---|---|---|---|---|
| 0 | 0 | Little-endian | Little-endian | Little-endian |
| 0 | 1 | Mixed-endian | Little-endian | Little-endian |
| 1 | X (don’t care) | ARM big-endian | ARM big-endian | ARM big-endian |
MPMCBSTRBENx is set HIGH to enable byte strobes on a port, and to indicate that a port is compliant with ARMv6 masters. The master provides byte strobes on the HBSTRB[7:0] lines. When set HIGH, the byte strobe signals are always used by the MPMC and therefore must be driven to the correct values on all transfers, regardless of the HUNALIGN value. The ARM11 drives the byte strobes in this way.
MPMCBSTRBENx is set LOW to indicate that a port is compliant with ARMv5 and earlier masters only. The endianness of the data transfers to and from the external memories is then ARMv5 little-endian or ARMv5 big-endian, determined by the state of the global endian mode signal, MPMCBIGENDIAN.
The power-on reset value of the global MPMCBIGENDIAN signal can be overridden through the register interface by accessing the MPMCConfig Register.
The setting of ARM11 mixed-endian mode for a port cannot be overridden through the register interface. It is fixed at power-on reset.
All data in the MPMC must be flushed when switching between little-endian and big-endian modes. This is so that data residing in the merge buffers is transferred correctly.
Memory transactions can be 8, 16, 32, or 64 bits wide. Any access attempted with a size greater than the width of the AHB memory ports causes an ERROR response on HRESP[0] and the transfer is terminated.
Accesses to address space within a memory bank which is not populated generates an ERROR response on HRESP[0] and the transfer is terminated. The system decoder defines the populated address space within a memory bank using a full decode of the corresponding HSELMPMCxCSy select signal.
The MPMC is not able to detect unpopulated memory areas, so the system decoder must fully define the memory map and ensure that the HSELMPMCxCSy signals are only driven when populated memory locations are addressed.
Write transactions to write-protected memory areas generate an ERROR response on HRESP[0] and the transfer is terminated.
The data ports are non-coherent, because there is no central buffer or transfer checking mechanism in the MPMC. This means that reads and writes to the same location in memory are only coherent when the data is available in the memory device.
For example, if a write is pending on a low priority port and a read from the same location is performed from a higher priority port which is granted before the write, the value returned is the data read from that address in memory, not the value pending to be written by the other port.
Devices which require coherency over different data ports must use a semaphore mechanism to indicate when data is available.
For an AHB master such as the ARM11 which has separate read and write data ports which much be coherent, disabling the AHB port buffer inserts wait states after a write transfer until the write is performed to memory. This ensures that a read to the same address following the write returns the value written to memory.
64-bit AHB ports provide support for the ARM11 AMBA extensions. This includes the following:
exclusive accesses using extended HPROT and HRESP lines
mixed-endian transfers using the HBSTRB byte strobe signals
unaligned transfers using the byte strobe and unalign signals:
HBSTRB
HUNALIGN.
For further information, see the Systems IP ARM11 AMBA (Rev 2.0) AHB Extensions v1.0 Specification.
Exclusive transfers use the HDOMAIN input to determine if transfers from different AHB ports are from the same master, for example, ARM11 read and write data ports. The 64-bit GXI port and 32-bit AHB ports are in a separate domain, because only 64-bit AHB ports can perform exclusive transfers.
Four exclusive transfer monitors are provided, with each monitor dedicated to a single domain. This enables four exclusive accesses from four different domains to four different addresses to be in progress at any one time.
| Copyright © 2003 ARM Limited. All rights reserved. | ARM DDI 0278B |
| Non-Confidential | |
| PDF version | |
| Home > Functional Overview > MPMC functional description > AHB slave memory interfaces |