| |||
| Home > Functional Overview > Low power operation | |||
In many systems, the contents of the memory system have to be maintained during low-power sleep modes. The MPMC provides two features to enable this:
dynamic memory refresh over soft reset
a mechanism to place the dynamic memories into self-refresh mode.
Self-refresh mode can be entered automatically by hardware or manually by software:
It can be entered manually setting the SREFREQ bit in the MPMCDynamicControl register and polling the SREFACK bit in the MPMCStatus register.
It can be entered automatically using a Power Management Unit (PMU). This is typically present to control the safe transition between the following modes:
power-up
reset
normal
sleep.
The PMU can be used to enable self-refresh mode to be entered automatically. To do this, the PMU asserts the MPMCSREFREQ signal when self-refresh mode is to be entered. The memory controller then closes any open memory banks and puts the external memory into self-refresh mode. The MPMC then asserts the MPMCSREFACK signal to indicate to the PMU that self-refresh mode is entered. The system must ensure that the memory subsystem is idle before asserting MPMCSREFREQ. The memory controller accepts transactions to dynamic memory even in self-refresh mode, if the accesses are targeted to chip selects that are populated with SyncFlash and its variants. This is required to aid booting from a SyncFlash device. Deasserting MPMCSREFREQ returns the memory to normal operation. See the memory data sheet for refresh requirements.
If MPMCSREFREQ is not required this signal must be tied LOW.
Static memory can be accessed as normal when the SDRAM memory is in self-refresh mode.