3.3.16. Dynamic Memory Last Data In To Read
Command Time Register
The four-bit, read/write, MPMCDynamictCDLR Register enables
you to program the last data in to read command time, tCDLR.
It is recommended that this register is modified during system initialization,
or when there are no current or outstanding transactions. This can
be ensured by waiting until the MPMC is idle, and then entering low-power
or disabled mode. This value is normally found in SDRAM data sheets
as tCDLR. This register is accessed with
one wait state.
Note
This register is used for all four dynamic memory chip selects.
Therefore the worse case value for all of the chip selects must
be programmed.
Figure 3.16 shows
the register bit assignments
Table 3.18 lists
the register bit assignments.
Table 3.18. MPMCDynamictCDLR Register bit assignments
| Bits | Name | Description |
|---|
| [31:4] | - | Read undefined. Write as zero. |
| [3:0] | Last data in to read command time (tCDLR) | 0x0-0xE =
n+1 clock cycles
0xF = 16 clock cycles
(reset value on nPOR)
|
PDF version