MultiPort Memory Controller (GX176) Technical Reference Manual 3.3.36. Additional Peripheral Identification Registers

3.3.36. Additional Peripheral Identification Registers

The MPMCPeriphID4-7 Registers are four eight-bit read-only registers, that span address locations 0xFD0-0xFDC. The registers can conceptually be treated as a single register that holds a 32-bit additional peripheral ID value.

Figure 3.36 shows the register bit assignments.

Figure 3.36. Conceptual MPMC Additional Peripheral ID Register bit assignments

Table 3.40 lists the register bit assignments.

Table 3.40. Conceptual MPMC Additional Peripheral ID Register bit assignments

Bits	Name	Description
[31:8]	-	Read undefined
[7:0]	Configuration1	Additional peripheral configuration information

The configuration options are peripheral-specific. The four, 8-bit Peripheral Identification Registers are described in the following subsections:

Additional Peripheral Identification Register 4

The MPMCPeriphID4 Register is hard-coded and the fields in the register determine the reset value.

Figure 3.37 shows the register bit assignments.

Figure 3.37. MPMCPeriphID4 Register bit assignments

Table 3.41 lists the register bit assignments.

Table 3.41. MPMCPeriphID4 Register bit assignments

Bits	Name	Description
[31:5]	-	Read undefined.
[4]	Configuration	MBX Interface Port: 0 = no 1 = yes For GX176, this field is set to 1.
[3:0]	Configuration	Number of memory ports: 0000-1111 = n + 1 memory ports 1001 = 10 memory ports (value for GX176).

Additional Peripheral Identification Register 5-7

The MPMCPeriphID5-7 Registers are reserved. Table 3.42 shows the bit assignments for the MPMCPeriphID5-7 Registers.

Table 3.42. MPMCPeriphID5-7 Register bit assignments

Bits	Name	Description
[31:0]	-	Read undefined.

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