MultiPort Memory Controller (GX176) Technical Reference Manual 3.3.25. Static Memory Write Delay Registers 0-3

3.3.25. Static Memory Write Delay Registers 0-3

The five-bit, read/write, MPMCStaticWaitWr0-3 Registers enable you to program the delay from the chip select to the write access. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the MPMC is idle, and then entering low-power or disabled mode. These registers are not used if the Extended Wait (EW) bit is enabled in the MPMCStaticConfig0-3 Registers. These registers are accessed with one wait state.

Figure 3.25 shows the register bit assignments.

Figure 3.25. MPMCStaticWaitWr0-3 Register bit assignments

Table 3.28 lists the register bit assignments.

Table 3.28. MPMCStaticWaitWr0-3 Register bit assignments

Bits	Name	Description
[31:5]	-	Read undefined. Write as zero.
[4:0]	Write wait states (WAITWR)	SRAM wait state time for write accesses after the first read:`0x00`-`0x1E` = (n + 2) HCLK cycle write access time^[1]`0x1F` = 33 HCLK cycle write access time (reset value on nPOR)
^[1]The wait state time for write accesses after the first read is WAITWR x t_HCLK

Copyright © 2003 ARM Limited. All rights reserved.	ARM DDI 0278B
Non-Confidential
PDF version