MultiPort Memory Controller (GX176) Technical Reference Manual 3.3.1. Control Register

3.3.1. Control Register

The MPMCControl Register is a two-bit, read/write register that controls the memory controller operation. The register fields can only be altered in idle state, when no external memory accesses are being performed. This register is accessed with zero wait states. Figure 3.1 shows the register bit assignments.

Figure 3.1. MPMCControl Register bit assignments

Table 3.2 lists the register bit assignments.

Table 3.2. MPMCControl Register bit assignments

Bits	Name	Description
[31:3]	-	Read undefined. Write as zero.
[2]	Low-power mode (L)	Indicates normal or low-power mode: 0 = normal mode (reset value on nPOR and HRESETn) 1 = low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by AHB, or power-on reset. You must only modify this bit when the MPMC is in idle state.^[1]^[2]
[1]	-	Read undefined. Write as zero.
[0]	MP Enable (E)	Indicates if the MPMC is enabled or disabled: 0 = disabled 1 = enabled (reset value on nPOR and HRESETn). Disabling the MPMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by system, or power-on reset. The MPMC produces an ERROR response (on HRESP) to external memory accesses when this bit is LOW. You must only modify this bit when the MPMC is in idle state.^ab
^[1]The external memory cannot be accessed in low-power and/or disable states. If a memory access is performed an error response is generated. ^[2]The memory controller AHB register programming port can be accessed normally. The MPMC registers can be programmed in low-power and disabled state.

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