MultiPort Memory Controller (GX176) Technical Reference Manual

Revision: r0p1

Table of Contents

About this document
Product revision status
Intended audience
Using this manual
Further reading
Feedback on the ARM MPMC (GX176)
Feedback on this document
1. Introduction
1.1. About the ARM MPMC (GX176)
1.1.1. Features of the MPMC
1.2. Supported dynamic memory devices
1.2.1. DDR-SDRAM devices
1.2.2. SDRAM devices
1.2.3. Micron style synchronous flash devices
1.2.4. Micron style V-synchronous flash devices
1.2.5. JEDEC low-power SDRAM devices
1.3. Supported static memory devices
1.3.1. Examples of ROM devices
1.3.2. Examples of page mode ROM devices
1.3.3. Examples of SRAM devices
1.3.4. Examples of flash devices
1.3.5. Examples of page mode flash devices
1.3.6. Examples of NAND flash memory devices
1.4. Product revisions
2. Functional Overview
2.1. MPMC functional description
2.1.1. Multiport memory controller block
2.1.2. AHB slave register interface
2.1.3. AHB slave memory interfaces
2.1.4. MBX Interface Port
2.1.5. Data buffers
2.1.6. Endian and packing logic
2.1.7. Arbiter
2.1.8. Memory controller state machine
2.1.9. Pad interface
2.1.10. Test Interface Controller (TIC)
2.2. Overview of a MPMC, ASIC, or ASSP system
2.2.1. External bus
2.2.2. Internal bus
2.3. AHB slave memory interface priority
2.3.1. AHB memory port latency
2.4. Low power operation
2.4.1. Low-power SDRAM deep sleep mode
2.4.2. Low-power SDRAM partial array refresh
2.5. Lock and semaphores
2.6. Burst types
2.7. Busy transfer type
2.8. Arbitration
2.8.1. Occurrence
2.8.2. Priority
2.8.3. AHB memory port latency
2.8.4. Arbitration strategy
2.9. Worst case transaction latency
2.9.1. Worst case transaction latency for the highest priority AHB memory port
2.9.2. Worst case transaction latency for the lower priority AHB memory ports
2.9.3. System factors affecting worst case latency
2.10. Sharing memory bandwidth between AHB ports
2.10.1. Typical AHB port TimeOut value given bandwidth requirement
2.10.2. Typical AHB port TimeOut value given percentage of memory bandwidth requirement
2.10.3. Typical AHB bandwidth requirement example
2.10.4. Typical AHB percentage bandwidth example
2.11. Memory bank select
2.12. Memory map
2.12.1. Chip select 1 static memory configuration
2.12.2. Chip select 5 SDRAM memory configuration
2.12.3. Boot from flash, SRAM remapped after boot
2.12.4. Example of a boot from flash, SDRAM remapped after boot
2.12.5. Memory aliasing
2.12.6. Unused AHB HADDRx address bits
2.12.7. External memory turnaround
2.13. Sharing memory interface signals
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Register summary
3.3. Register descriptions
3.3.1. Control Register
3.3.2. Status Register
3.3.3. Configuration Register
3.3.4. Dynamic Memory Control Register
3.3.5. Dynamic Memory Refresh Timer Register
3.3.6. Dynamic Memory Read Configuration Register
3.3.7. Dynamic Memory Precharge Command Period Register
3.3.8. Dynamic Memory Active To Precharge Command Period Register
3.3.9. Dynamic Memory Self-refresh Exit Time Register
3.3.10. Dynamic Memory Write Recovery Time Register
3.3.11. Dynamic Memory Active To Active Command Period Register
3.3.12. Dynamic Memory Auto-refresh Period Register
3.3.13. Dynamic Memory Exit Self-refresh Register
3.3.14. Dynamic Memory Active Bank A-B Time Register
3.3.15. Dynamic Memory Load Mode Register
3.3.16. Dynamic Memory Last Data In To Read Command Time Register
3.3.17. Static Memory Extended Wait Register
3.3.18. Dynamic Memory Configuration Registers 0-3
3.3.19. Dynamic Memory RAS and CAS Delay Registers 0-3
3.3.20. Static Memory Configuration Registers 0-3
3.3.21. Static Memory Write Enable Delay Registers 0-3
3.3.22. Static Memory Output Enable Delay Registers 0-3
3.3.23. Static Memory Read Delay Registers 0-3
3.3.24. Static Memory Page Mode Read Delay Registers 0-3
3.3.25. Static Memory Write Delay Registers 0-3
3.3.26. Static Memory Turnaround Delay Registers 0-3
3.3.27. NAND Memory Control Vector Register
3.3.28. NAND Memory Address Vectors 1-4 Register
3.3.29. NAND Memory Address Vector 5 Register
3.3.30. NAND Memory Timing Value 1 Register
3.3.31. NAND Memory Timing Value 2 Register
3.3.32. NAND Status Information Register
3.3.33. AHB Control Registers 0-8
3.3.34. AHB Status Registers 0-8
3.3.35. AHB Timeout Registers 0-8
3.3.36. Additional Peripheral Identification Registers
3.3.37. Peripheral Identification Registers
3.3.38. PrimeCell Identification Registers 0-3
4. Programmer’s Model for Test
4.1. MPMC test harness overview
4.1.1. AMBA test strategy
4.1.2. Non-AMBA intra-chip integration test strategy
4.1.3. Primary I/O test strategy
4.2. Production test
4.3. Test registers
4.3.1. Test Control Register
4.3.2. Test Input 1 Register
4.3.3. Test Input 2 Register
4.3.4. Test Output Register
4.3.5. Test Scratch Register
A. Signal Descriptions
A.1. AHB register signals
A.2. AHB memory signals
A.3. MBX Interface Port signals
A.4. Miscellaneous signals
A.4.1. Tie-off signals
A.4.2. Test signals
A.4.3. Clock and reset signals
A.4.4. DLL and self-refresh signals
A.4.5. External Bus Interface signals
A.5. Pad interface and control signals
A.6. Test Interface Controller (TIC) AHB signals
A.7. Scan test signals

List of Figures

1. Key to timing diagram conventions
2.1. MPMC block diagram
2.2. 64-bit master to 32-bit slave register interface downsizer
2.3. 32-bit master to 64-bit slave memory interface
2.4. MBX 3D Graphics Core read, five transactions
2.5. MBX 3D Graphics Core read, multiple transactions
2.6. MBX 3D Graphics Core read, paused
2.7. MBX 3D Graphics Core read, stalled
2.8. MBX 3D Graphics Core write, eight transactions
2.9. MBX 3D Graphics Core write, five transactions
2.10. MBX 3D Graphics Core write, six transactions
2.11. MBX 3D Graphics Core read/write transactions
2.12. GBSTRB timing diagram
2.13. Pad interface block diagram
2.14. TIC block diagram
2.15. MPMC (GX176) in an example system
3.1. MPMCControl Register bit assignments
3.2. MPMCStatus Register bit assignments
3.3. MPMCConfig Register bit assignments
3.4. MPMCDynamicControl Register bit assignments
3.5. MPMCDynamicRefresh Register bit assignments
3.6. MPMCDynamicReadConfig Register bit assignments
3.7. MPMCDynamictRP Register bit assignments
3.8. MPMCDynamictRAS Register bit assignments
3.9. MPMCDynamictSREX Register bit assignments
3.10. MPMCDynamictWR Register bit assignments
3.11. MPMCDynamictRC Register bit assignments
3.12. MPMCDynamictRFC Register bit assignments
3.13. MPMCDynamictXSR Register bit assignments
3.14. MPMCDynamictRRD Register bit assignments
3.15. MPMCDynamictMRD Register bit assignments
3.16. MPMCDynamictCDLR Register bit assignments
3.17. MPMCStaticExtendedWait Register bit assignments
3.18. MPMCDynamicConfig0-3 Register bit assignments
3.19. MPMCDynamicRasCas0-3 Register bit assignments
3.20. MPMCStaticConfig0-3 Register bit assignments
3.21. MPMCStaticWaitWen0-3 Register bit assignments
3.22. MPMCStaticWaitOen0-3 Register bit assignments
3.23. MPMCStaticWaitRd0-3 Register bit assignments
3.24. MPMCStaticWaitPage0-3 Register bit assignments
3.25. MPMCStaticWaitWr0-3 Register bit assignments
3.26. MPMCStaticWaitTurn0-3 Register bit assignments
3.27. MPMCNANDControl Register bit assignments
3.28. MPMCNANDAddress1 Register bit assignments
3.29. MPMCNANDAddress2 Register bit assignments
3.30. MPMCNANDTiming1Register bit assignments
3.31. MPMCNANDTiming2Register bit assignments
3.32. MPMCNANDStatus Register bit assignments
3.33. MPMCAHBControl0-8 Register bit assignments
3.34. MPMCAHBStatus0-8 Register bit assignments
3.35. MPMCAHBTimeOut0-8 Register bit assignments
3.36. Conceptual MPMC Additional Peripheral ID Register bit assignments
3.37. MPMCPeriphID4 Register bit assignments
3.38. Peripheral identification register bit assignment
3.39. Conceptual PrimeCell ID Register bit assignments
4.1. MPMCITCR Register bit assignments
4.2. MPMCITIP1 Register bit assignments
4.3. MPMCITIP2 Register bit assignments
4.4. MPMCITOP Register bit assignments

List of Tables

2.1. MPMC endianness options
2.2. GBSTRB bits
2.3. GBSTRB transactions
2.4. Example ARM MBX HR-S memory transfer profile
2.5. Read buffer enabled
2.6. Read buffer disabled
2.7. Read buffer enabled 
2.8. Read buffer disabled
2.9. Write buffer enabled
2.10. Write buffer disabled
2.11. Write buffer enabled
2.12. Write buffer disabled
2.13. Memory bank selection
3.1. MPMC register summary
3.2. MPMCControl Register bit assignments
3.3. MPMCStatus Register bit assignments
3.4. MPMCConfig Register bit assignments
3.5. MPMCDynamicControl Register bit assignments
3.6. Output voltage settings
3.7. MPMCDynamicRefresh Register bit assignments
3.8. MPMCDynamicReadConfig Register bit assignments
3.9. MPMCDynamictRP Register bit assignments
3.10. MPMCDynamictRAS Register bit assignments
3.11. MPMCDynamictSREX Register bit assignments
3.12. MPMCDynamictWR Register bit assignments
3.13. MPMCDynamictRC Register bit assignments
3.14. MPMCDynamictRFC Register bit assignments
3.15. MPMCDynamictXSR Register bit assignments
3.16. MPMCDynamictRRD Register bit assignments
3.17. MPMCDynamictMRD Register bit assignments
3.18. MPMCDynamictCDLR Register bit assignments
3.19. MPMCStaticExtendedWait Register bit assignments
3.20. MPMCDynamicConfig0-3 Register bit assignments
3.21. Address mapping
3.22. MPMCDynamicRasCas0-3 Register bit assignments
3.23. MPMCStaticConfig0-3 Register bit assignments
3.24. MPMCStaticWaitWen0-3 Register bit assignments
3.25. MPMCStaticWaitOen0-3 Register bit assignments
3.26. MPMCStaticWaitRd0-3 Register bit assignments
3.27. MPMCStaticWaitPage0-3 Register bit assignments
3.28. MPMCStaticWaitWr0-3 Register bit assignments 
3.29. MPMCStaticWaitTurn0-3 Register bit assignments
3.30. MPMCNANDControl Register bit assignments
3.31. MPMCNANDAddress1 Register bit assignments
3.32. MPMCNANDAddress2 Register bit assignments
3.33. MPMCNANDTiming1Register bit assignments
3.34. MPMCNANDTiming2Register bit assignments
3.35. MPMCNANDStatus Register bit assignments
3.36. MPMCAHBControl0-8 Register bit assignments
3.37. Transfer types
3.38. MPMCAHBStatus0-8 Register bit assignments
3.39. MPMCAHBTimeOut0-8 Register bit assignments
3.40. Conceptual MPMC Additional Peripheral ID Register bit assignments
3.41. MPMCPeriphID4 Register bit assignments
3.42. MPMCPeriphID5-7 Register bit assignments
3.43. Conceptual MPMC Peripheral ID Register bit assignments
3.44. MPMCPeriphID0 Register bit assignments
3.45. MPMCPeriphID1 Register bit assignments
3.46. MPMCPeriphID2 Register bit assignments
3.47. MPMCPeriphID3 Register bit assignments
3.48. Conceptual PrimeCell ID Register bit assignments
4.1. Test registers memory map
4.2. MPMCITCR Register bit assignments
4.3. MPMCITIP1 Register bit assignments
4.4. MPMCITIP2 Register bit assignments
4.5. MPMCITOP Register bit assignments
4.6. MPMCITScratch Register bit assignments
A.1. AHB register signal descriptions
A.2. AHB memory signal descriptions
A.3. MBX Interface Port signals
A.4. Tie-off signal descriptions
A.5. Test signal descriptions
A.6. Clock and reset signal descriptions
A.7. DLL and self-refresh signal descriptions
A.8. EBI signal descriptions
A.9. Pad interface and control signal descriptions
A.10. TIC signal descriptions
A.11. Scan test signal descriptions

Proprietary Notice

The content of this document is proprietary to ARM Limited and Imagination Technologies Limited. It may not be copied or its contents disclosed without prior consent.

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

MBX™ and the MBX™ trademark are owned by Imagination Technologies Limited and used by ARM under license.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A28 August 2003First release
Revision B17 October 2003Update for r0p1
Copyright © 2003 ARM Limited. All rights reserved.ARM DDI 0278B