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Table A.11 shows the cache controller MBIST inputs and outputs.
Table A.11. Cache controller MBIST block inputs and outputs
| Signal | Input/ output | Notes |
|---|---|---|
| MBISTDOUT[63:0] | Input | MBIST data out, to cache controller MBISTDOUT[63:0] = MBIST data out for data RAM MBISTDOUT[31:0] = MBIST data out for data parity RAM MBISTDOUT[19:0] = MBIST data out for tag RAM MBISTDOUT[15:0] = MBIST data out for dirty RAM |
| MBISTADDR[17:0] | Output | MBIST address MBISTADDR[17:0] used for data RAM, two LSBs used as doubleword select MBISTADDR[17:2] used for data parity RAM MBISTADDR[14:2] used for Tag and Dirty RAMs |
| MBISTCE[10:0] | Output | MBIST RAM Chip Enables, for writes MBISTCE[0] = data RAM chip enable MBISTCE[1] = tag RAM 0 chip enable MBISTCE[2] = tag RAM 1 chip enable MBISTCE[3] = tag RAM 2 chip enable MBISTCE[4] = tag RAM 3 chip enable MBISTCE[5] = tag RAM 4 chip enable MBISTCE[6] = tag RAM 5 chip enable MBISTCE[7] = tag RAM 6 chip enable MBISTCE[8] = tag RAM 7 chip enable MBISTCE[9] = dirty RAM chip enable MBISTCE[10] = data parity RAM chip enable |
| MBISTDCTL[12:0] | Output | MBIST Control, for reads MBISTDCTL[1:0] = MBIST data select for 64 bits of 256-bit wide data RAM MBISTDCTL[2] = MBIST RAM select for Data RAM MBISTDCTL[3] = MBIST RAM select for tag RAM 0 MBISTDCTL[4] = MBIST RAM select for tag RAM 1 MBISTDCTL[5] = MBIST RAM select for tag RAM 2 MBISTDCTL[6] = MBIST RAM select for tag RAM 3 MBISTDCTL[7] = MBIST RAM select for tag RAM 4 MBISTDCTL[8] = MBIST RAM select for tag RAM 5 MBISTDCTL[9] = MBIST RAM select for tag RAM 6 MBISTDCTL[10] = MBIST RAM select for tag RAM 7 MBISTDCTL[11] = MBIST RAM select for dirty RAM MBISTDCTL[12] = MBIST RAM select for data parity RAM |
| MBISTDIN[63:0] | Output | MBIST data in, to cache controller MBISTDIN[63:0] = MBIST data in for data RAM MBISTDIN[31:0] = MBIST data in for data parity RAM MBISTDIN[19:0] = MBIST data in for tag RAM MBISTDIN[15:0] = MBIST data in for dirty RAM |
| MBISTWE | Output | MBIST Write Enable |
| MTESTON | Output | MBIST Mode Enable |
| Copyright © 2003-2006 ARM Limited. All rights reserved. | ARM DDI 0284G |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > Cache controller signals > Cache controller MBIST interface |