B.1.2. Unregistered signals

The unregistered input signals are:

The unregistered output signals are:

Figure B.1 shows the cache controller target timing parameters for unregistered signals. The timing parameter T is the internal clock latency of the clock buffer tree, dependent on process technology and design parameters. Timing parameters ending with suffix h represent hold times. Timing parameters ending with suffix d represent delay times. Contact your silicon supplier for more details.

Figure B.1. Target timing parameters for unregistered signals


Actual clock frequencies and input and output timing constraints vary according to application requirements and the silicon process technologies used. The maximum operating clock frequencies attained by ARM devices increases over time as a result.

Copyright © 2003-2006 ARM Limited. All rights reserved.ARM DDI 0284G