2.3.3. Control Register

The Control Register, register 1, must be accessed using a read-modify-write sequence. Figure 2.3 shows the format of the Control Register.

Figure 2.3. Control Register

Table 2.6 shows the encodings of the Control Register.

Table 2.6. Control Register

[0]Unified cache enable

0 = Cache in bypass mode, default

1 = Cache is enabled.


Any change to the cache enable bit is seen by slave ports only at the start of a new transaction. If the bit is changed while a transaction is on going on a slave port, that transaction completes as if the enable bit did not change, so an ongoing linefill, and possible subsequent line eviction, completes even if the cache is turned off.

Copyright © 2003-2006 ARM Limited. All rights reserved.ARM DDI 0284G