2.3.3. Control Register

The Control Register, register 1, must be accessed using a read-modify-write sequence. Figure 2.3 shows the format of the Control Register.

Figure 2.3. Control Register

Table 2.6 shows the encodings of the Control Register.

Table 2.6. Control Register

BitFieldDescription
[31:1]ReservedSBZ
[0]Unified cache enable

0 = Cache in bypass mode, default

1 = Cache is enabled.

Note

Any change to the cache enable bit is seen by slave ports only at the start of a new transaction. If the bit is changed while a transaction is on going on a slave port, that transaction completes as if the enable bit did not change, so an ongoing linefill, and possible subsequent line eviction, completes even if the cache is turned off.

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