| Copyright © 2003-2006 ARM Limited. All rights reserved. | ARM DDI 0284G |
| Non-Confidential | |
 PDF version | |
| Home > Design for Test > About design for test |
| |||
| Home > Design for Test > About design for test | |||
To guarantee signal integrity with the AHB and RAM interfaces, all inputs and outputs of the cache controller are registered, with these exceptions:
nRESET, nHRESET
CLKENS0, CLKENS1, and CLKENS2
HCLKENM0, HCLKENM1, and HCLKENM2
HREADYM0, HREADYM1, HREADYM2, HREADYS0, HREADYS1, and HREADYS2
HRESPS0, HRESPS1, and HRESP2
DATARD, DATAPRD, and DATAERR.
This simplifies scan testing of the block, and full scan testing is supported.
| Copyright © 2003-2006 ARM Limited. All rights reserved. | ARM DDI 0284G |
| Non-Confidential | |
| PDF version | |
| Home > Design for Test > About design for test |