4.3. Idle

The output signal IDLE indicates when the cache controller is not doing any internal processing. That is, all linefill buffers have been written to data RAM, the eviction buffer is empty, and there are no requests being processed. At this point, IDLE is asserted.

The write buffer may not be empty when the IDLE signal is set. If you assert IDLE to switch to wait for interrupt mode, drain the write buffer first.

If the L1 core has entered a wait for interrupt state, and now the cache controller is idle, the clock to both the L1 core and cache controller can be stopped. The cache controller must now be awoken at the same time or before the L1 core, so that any AHB requests from the L1 core are handled by the cache controller.

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