2.9. External abort support for L3 memory

The cache controller gives limited support for external aborts, because of restrictions of the AHB protocol. There are methods to acknowledge all external aborts created by a slave device:

The following support is supplied by the cache controller, assuming the slave main memory holds a copy of the aborting address.

If an ERROR response is received by the cache controller on a master port HRESPMx:

In this way, all L3 external aborts can be detected at level 1.

Note

If a noncacheable known-length burst is early terminated on a slave port, the behavior of the master port handling the transaction is unpredictable.

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