The abort-generating slave must keep a copy of the aborting address. This means the master, after receiving the external abort, whether precise or imprecise, can deduce the aborting address by reading the appropriate slave register.

The cache controller is a slave to an ARM1136 core, but a master to the main memory system. In effect this means that the cache controller is just a method to communicate between the master core and the slave main memory.

The AHB protocol does not provide a method for passing back an ERROR response that is not combined with its original transaction.

If this request was a noncacheable read, or nonbufferable write, using ARM v5 nomenclature, then the associated slave port has been waited until the response was received from the main memory. The ERROR response is passed through to L1 on the appropriate word.

If the request was a cacheable read which missed at L2, then the ERROR response is passed through to L1 on the appropriate word, and the line is not marked as valid in the L2.

If the request was a bufferable write, then the slave port completes its transaction before the ERROR response is received from main memory. The AHB protocol does not permit this response to be passed back to L1. In this case, the cache controller produces a pulse on the Event bus. See Appendix C Event Monitor for details. If there is an event monitor, it can then produce an interrupt to the L1 core.