2.3.4. Auxiliary Control Register

Figure 2.4 shows the format of the Auxiliary Control Register.

Figure 2.4. Auxiliary Control Register format

Table 2.7 shows the encodings for the Auxiliary Control Register.

Table 2.7. Auxiliary Control Register

[24]Exclusive abort disable

0 = The cache controller sends an ERROR response back to exclusive access in a cacheable, shared memory region with shared override bit set, default

1 = abort generation for exclusive access disabled. Treated as cacheable non-shared accesses.

[23]Write allocate override

0 = Use of HPROT attributes, default

1 = Override HPROT attributes. All Write-Through and write-back accesses are read-write-allocate.

[22]Shared attribute override enable

0 = Shared accesses treated as noncacheable, default

1 = Shared attribute internally ignored but still forwarded to L3 memory.

[21]Parity enable

0 = Disabled, default

1 = Enabled.

[20]Event bus enable

0 = Disabled, default

1 = Enabled.

[19:17]Way size

0b000 Reserved, and internally mapped to 16KB

0b001 16KB, default

0b010 32KB

0b011 64KB

0b100 128KB

0b101 256KB

0b110-0b111 Reserved, and internally mapped to 256KB.


0b0000 Cache absent, default

0b0001 direct-mapped cache

0b0010 2-way cache

0b0011 3-way cache

0b0100 4-way cache

0b0101 5-way cache

0b0110 6-way cache

0b0111 7-way cache

0b1000 8-way cache

0b1001-0b1111 Reserved, and internally mapped to 8-way associativity.

[12]Wrap, accesses disable

0 = Master ports can perform wrap accesses, default.

1 = Wrap accesses requested on slave ports are converted to linear accesses on master ports.

[11:9]Latency for dirty RAM

0b000 1 cycle of latency, no additional latency

0b001 2 cycles of latency

0b010 3 cycles of latency

0b011 4 cycles of latency

0b100 5 cycles of latency

0b101 6 cycles of latency

0b110 7 cycles of latency

0b111 8 cycles of latency, default.

The output signals DIRTYLAT[2:0], TAGLAT[2:0], WDATALAT[2:0], and RDATALAT[2:0] reflect the values set in the Auxiliary Control Register in the respective fields. See Miscellaneous signals.

[8:6]Latency for tag RAMs
[5:3]Latency for data RAM writes
[2:0]Latency for data RAM reads
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