2.3.7. Uses of Lockdown Format C

Lockdown format C, used in the ARM926EJ-S, ARM1026, and ARM1136 caches, provides a method to restrict the replacement algorithm used on cache linefills and to only use selected cache ways within a set. Using this method, code can be fetched or loaded into the cache controller and protected from being evicted.

Note

A noncacheable routine is a software loop noncacheable at L2 in order to prevent cache pollution. It is executed by the CPU, and reads at least one word out of 8, L2 cache line size, in the data pool or code pool that is intended to be put in the L2 cache.

Preventing or reducing cache pollution

There can be benefits in having a critical piece of software or data being cached at the cache controller with the insurance that it cannot be polluted or evicted, due to a new allocation. Using lockdown format C provides a simple method to load data into the cache controller using the linefill mechanism, then locking the cache memory to prevent eviction, and finally using the cache controller cache maintenance operations to efficiently clean the data to the main memory system.

To do that:

  1. Use lockdown format C (I and/or D lockdown) to restrict the permitted ways for cache filling to n-ways, where n is less than the total number of ways. For example only permit filling to way 0.

  2. Cache code or data into the cache

    • Fetch code into the cache by executing the routine for the first time.

    • Load data into the cache by:

      • loading data for the first time

      • cache the data in the cache controller by executing the read loop being cached at L1 only.

  3. Write to the lockdown register, I and/or D lockdown, to prevent allocation to way 0, but enable allocation to ways 1-7. The code or data is now protected in the cache and cannot be evicted on a linefill.

Using Lockdown Format C with the cache controller for processing frame buffers

There might be benefits in processing large frame buffers in the cache controller, and making them appear as if there is a large amount of restricted physically addressed space available in fast memory. Because the cache controller is eight-way set associative, using lockdown format C provides a simple method to:

  1. Load data into the cache controller using the linefill mechanism

  2. Lock the cache memory to prevent eviction

  3. Use the cache controller cache maintenance operations to efficiently clean the data to the main memory system.

Consider the example of requiring a 1MB frame buffer in the 2MB 8-way set associative cache controller, in a system using ARM1136 AMBA extensions with ARMv6 architecture.

  1. Set the address page attributes so the L1 page is noncacheable and the L2 page is cacheable.

  2. Set the cache controller lockdown to only fill to ways 0-3 (=1MB).

  3. The 1MB is now contiguously mapped over four ways of 256KB each.

  4. Load data into the cache controller by executing a load routine in an ARM1136 core, where a series of LDRs are issued, one cache line apart from one another. The L1 memory attribute is noncacheable, so the L1 cache is not polluted. The cache controller memory attribute is cacheable, so the cache controller performs linefills, filling into ways 0-3. The linefill buffer in the cache controller provides efficient filling.

  5. When finished, set the cache controller lockdown to lock ways 0-3, and only enable filling to ways 4-7 (=1MB).

The cache controller now contains a 1MB frame buffer, and 1MB of four-way associative cache. Lookups and reads or writes can occur to the entire 2MB, but the frame buffer is prevented from being evicted. Cache maintenance operations can be used to efficiently clean to main memory. When the frame buffer is no longer required, ways 0-3 can be unlocked, and are naturally overwritten. Lockdown format C has a pattern-matching field, so any of the eight ways can be locked. There is no requirement to start at 0 and work up. If all ways are marked as being locked, then nothing is allocated.

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