2.5. Register 15: Test and Debug

The Test Operation Register enables the contents of the cache controller to be read and written.

For cache line read, test operation is written with the nRW bit cleared so that the content of the line designated by the Index Way combination fields is put in the line data registers and its attributes put in the Line Tag Register. All information needed about the cache line can then be retrieved by reading Line Data and Line Tag Registers.

For cache line writes, all line data and attributes must be written first in both the Line Data Registers and Line Tag Registers. At this time, by writing to the Test Operation Register, the cache line designated by the Index Way combination fields is updated with register contents.

The Test Operation Register is stored in Index Way combination format as shown in Figure 2.8. Index field size depends on cache way size.

Figure 2.8. Test operation format

Figure 2.9 shows the order in which words are stored in a cache line.

Figure 2.9. Word order in cache lines

Figure 2.10 shows the Line Tag Register.

Figure 2.10. Line Tag Register format

Table 2.10 shows the Line Tag Register mapping.

Table 2.10. Line Tag Register mapping



An invalid line always has its tag set to zero until it has been written through a test operation


Dirty 1

Defines state of the last four words in the cache line, words 4-8


Dirty 0

Defines state of the first four words in the cache line, words 0-3


Victim pointer

Defines last allocated way

b111 represents way 7

b000 represents way 0


Address BASE + 0xF10 stands for Word 0 in the line, up to Base + 0xF2C which stands for Word 8.

Copyright © 2003-2006 ARM Limited. All rights reserved.ARM DDI 0284G